mac_rx_ctrl.v

verilog实现的异步UART代码

            State_FFFullDrop:
                    if (!Crs_dv)                        
                        Next_state  =State_IFG;     
                    else                                
                        Next_state  =Current_state;                                                
            State_FFFullErrEnd:
                        Next_state  =State_FFFullDrop;                                        
            State_IFG:                                  
                    if (IFG_counter==RX_IFG_SET-4)   //remove some additional time     
                        Next_state  =State_idle;        
                    else                                
                        Next_state  =Current_state;     
                                                        
            default:                                    
                        Next_state  =State_idle;        
        endcase                                         
                     
                                                        
always @ (posedge Reset or posedge Clk)                 
    if (Reset)                                          
        IFG_counter     <=0;   
    else if (Current_state!=State_IFG)
        IFG_counter     <=0;                                
    else 
        IFG_counter     <=IFG_counter + 1;
//******************************************************************************
//gen fifo interface signals                                                     
//******************************************************************************                     

assign  Fifo_data   =RxD_dl1;       

always @(Current_state)
    if  (Current_state==State_data)
        Fifo_data_en        =1;
    else
        Fifo_data_en        =0;
        
always @(Current_state)
    if  (Current_state==State_ErrEnd||Current_state==State_OkEnd
         ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Fifo_data_end       =1;
    else
        Fifo_data_end       =0;

always @(Current_state)
    if  (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Fifo_data_err       =1;
    else
        Fifo_data_err       =0;     

//******************************************************************************
//CRC_chk interface                                               
//****************************************************************************** 

always @(Current_state)
    if (Current_state==State_data)
        CRC_en  =1;
    else
        CRC_en  =0;
        
always @(Current_state)
    if (Current_state==State_SFD)
        CRC_init    =1;
    else
        CRC_init    =0;
        
//******************************************************************************
//gen rmon signals                                         
//******************************************************************************    
always @ (posedge Clk or posedge Reset)
    if (Reset)  
        Frame_length_counter        <=0;
    else if (Current_state==State_SFD)
        Frame_length_counter        <=1;
    else if (Current_state==State_data)
        Frame_length_counter        <=Frame_length_counter+ 1'b1;
        
always @ (Frame_length_counter or RX_MIN_LENGTH)
    if (Frame_length_counter<RX_MIN_LENGTH)
        Too_short   =1;
    else
        Too_short   =0;
        
always @ (*)
    if (Frame_length_counter>RX_MAX_LENGTH)
        Too_long    =1;
    else
        Too_long    =0;
        
assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;

always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon_tmp   <=0; 
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon_tmp   <=1;        
    else
        Rx_apply_rmon_tmp   <=0; 
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon_tmp_pl1   <=0;
    else
        Rx_apply_rmon_tmp_pl1   <=Rx_apply_rmon_tmp;        

always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon   <=0; 
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon   <=1;        
    else if (Rx_apply_rmon_tmp_pl1)
        Rx_apply_rmon   <=0; 
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_pkt_err_type_rmon    <=0;
    else if (Current_state==State_CRCErrEnd)
        Rx_pkt_err_type_rmon    <=3'b001    ;//
    else if (Current_state==State_FFFullErrEnd)
        Rx_pkt_err_type_rmon    <=3'b010    ;// 
    else if (Current_state==State_ErrEnd)
        Rx_pkt_err_type_rmon    <=3'b011    ;//
    else if(Current_state==State_OkEnd)
        Rx_pkt_err_type_rmon    <=3'b100    ;


        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_pkt_type_rmon        <=0;
    else if (Current_state==State_OkEnd&&pause_frame_ptr)
        Rx_pkt_type_rmon        <=3'b100    ;//
    else if(Current_state==State_SFD&&Next_state==State_data)
        Rx_pkt_type_rmon        <={1'b0,MRxD[7:6]};

always @ (posedge Clk or posedge Reset)
    if (Reset)
        broadcast_ptr   <=0;
    else if(Current_state==State_IFG)
        broadcast_ptr   <=0;
    else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)
        broadcast_ptr   <=1;

        
    
//******************************************************************************
//MAC add checker signals                                                              
//******************************************************************************
always @ (Frame_length_counter or Fifo_data_en)
    if(Frame_length_counter>=1&&Frame_length_counter<=6)
        MAC_add_en  <=Fifo_data_en;
    else
        MAC_add_en  <=0;

//******************************************************************************
//flow control signals                                                            
//******************************************************************************
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Pause_current   <=Pause_idle;
    else
        Pause_current   <=Pause_next;
        
always @ (*)
    case (Pause_current)
        Pause_idle  : 
            if(Current_state==State_SFD)
                Pause_next  =Pause_pre_syn;
            else
                Pause_next  =Pause_current;
        Pause_pre_syn:
            case (Frame_length_counter)
                16'd1:  if (RxD_dl1==8'h01)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd2:  if (RxD_dl1==8'h80)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;            
                16'd3:  if (RxD_dl1==8'hc2)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd4:  if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd5:  if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd6:  if (RxD_dl1==8'h01)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd13: if (RxD_dl1==8'h88)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd14: if (RxD_dl1==8'h08)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd15: if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd16: if (RxD_dl1==8'h01)
                            Pause_next  =Pause_quanta_hi;
                        else
                            Pause_next  =Pause_idle;
                default:    Pause_next  =Pause_current;
            endcase
        Pause_quanta_hi :
            Pause_next  =Pause_quanta_lo;
        Pause_quanta_lo :
            Pause_next  =Pause_syn; 
        Pause_syn       :
            if (Current_state==State_IFG)
                Pause_next  =Pause_idle;
            else
                Pause_next  =Pause_current;
        default
            Pause_next  =Pause_idle;
    endcase

always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_h      <=0;
    else if(Pause_current==Pause_quanta_hi)
        pause_quanta_h      <=RxD_dl1;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta        <=0;
    else if(Pause_current==Pause_quanta_lo)
        pause_quanta        <={pause_quanta_h,RxD_dl1};
        
always @ (posedge Clk or posedge Reset)
    if (Reset)      
        pause_quanta_val_tmp    <=0;
    else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)
        pause_quanta_val_tmp    <=1;
    else
        pause_quanta_val_tmp    <=0;
        
always @ (posedge Clk or posedge Reset)
    if (Reset)      
        pause_quanta_val    <=0;
    else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)
        pause_quanta_val    <=1;
    else
        pause_quanta_val    <=0;        
    
always @ (posedge Clk or posedge Reset)
    if (Reset)  
        pause_frame_ptr     <=0;
    else if(Pause_current==Pause_syn)
        pause_frame_ptr     <=1;
    else
        pause_frame_ptr     <=0;
                
endmodule