📄 sd_rfrsh.rpt
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Device-Specific Information: d:\newsdram\sd_rfrsh.rpt
sd_rfrsh
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 fresh_req
| +----------------------------- LC26 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node1
| | +--------------------------- LC27 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node2
| | | +------------------------- LC28 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node3
| | | | +----------------------- LC29 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node4
| | | | | +--------------------- LC30 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node5
| | | | | | +------------------- LC31 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node6
| | | | | | | +----------------- LC32 |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node7
| | | | | | | | +--------------- LC22 |lpm_add_sub:73|addcore:adder|addcore:adder1|result_node0
| | | | | | | | | +------------- LC23 |lpm_add_sub:73|addcore:adder|addcore:adder1|result_node1
| | | | | | | | | | +----------- LC25 |lpm_add_sub:73|addcore:adder|addcore:adder1|result_node2
| | | | | | | | | | | +--------- LC18 rfrsh_cntr10
| | | | | | | | | | | | +------- LC19 rfrsh_cntr9
| | | | | | | | | | | | | +----- LC20 rfrsh_cntr8
| | | | | | | | | | | | | | +--- LC21 rfrsh_cntr7
| | | | | | | | | | | | | | | +- LC24 rfrsh_cntr0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - - - - - - - | - * | <-- fresh_req
LC32 -> - - - - - - - - - - - - - - * - | - * | <-- |lpm_add_sub:73|addcore:adder|addcore:adder0|result_node7
LC22 -> - - - - - - - - - - - - - * - - | - * | <-- |lpm_add_sub:73|addcore:adder|addcore:adder1|result_node0
LC23 -> - - - - - - - - - - - - * - - - | - * | <-- |lpm_add_sub:73|addcore:adder|addcore:adder1|result_node1
LC25 -> - - - - - - - - - - - * - - - - | - * | <-- |lpm_add_sub:73|addcore:adder|addcore:adder1|result_node2
LC18 -> * - - - - - - - - - * - - - - - | - * | <-- rfrsh_cntr10
LC19 -> * - - - - - - - - * * - - - - - | - * | <-- rfrsh_cntr9
LC20 -> * - - - - - - - * * * - - - - - | - * | <-- rfrsh_cntr8
LC21 -> * - - - - - - * * * * - - - - - | - * | <-- rfrsh_cntr7
LC24 -> * * * * * * * * * * * - - - - * | - * | <-- rfrsh_cntr0
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
4 -> * - - - - - - - - - - * * * * * | * * | <-- fresh_cycle
1 -> - - - - - - - - - - - - - - - - | - - | <-- rst_l
LC4 -> * - - - - - * * * * * - - - - - | - * | <-- rfrsh_cntr6
LC5 -> * - - - - * * * * * * - - - - - | - * | <-- rfrsh_cntr5
LC9 -> * - - - * * * * * * * - - - - - | - * | <-- rfrsh_cntr4
LC6 -> * - - * * * * * * * * - - - - - | - * | <-- rfrsh_cntr3
LC7 -> * - * * * * * * * * * - - - - - | - * | <-- rfrsh_cntr2
LC8 -> * * * * * * * * * * * - - - - - | - * | <-- rfrsh_cntr1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\newsdram\sd_rfrsh.rpt
sd_rfrsh
** EQUATIONS **
clk : INPUT;
fresh_cycle : INPUT;
rst_l : INPUT;
-- Node name is 'fresh_req' = ':72'
-- Equation name is 'fresh_req', type is output
fresh_req = DFFE( _EQ001 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ001 = !fresh_cycle & !rfrsh_cntr0 & !rfrsh_cntr1 & !rfrsh_cntr2 &
rfrsh_cntr3 & !rfrsh_cntr4 & !rfrsh_cntr5 & !rfrsh_cntr6 &
!rfrsh_cntr7 & !rfrsh_cntr8 & !rfrsh_cntr9 & !rfrsh_cntr10
# !fresh_cycle & fresh_req;
-- Node name is ':52' = 'rfrsh_cntr0'
-- Equation name is 'rfrsh_cntr0', location is LC024, type is buried.
rfrsh_cntr0 = DFFE( _EQ002 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ002 = !fresh_cycle & !rfrsh_cntr0;
-- Node name is ':51' = 'rfrsh_cntr1'
-- Equation name is 'rfrsh_cntr1', location is LC008, type is buried.
rfrsh_cntr1 = DFFE( _EQ003 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ003 = !fresh_cycle & _LC026;
-- Node name is ':50' = 'rfrsh_cntr2'
-- Equation name is 'rfrsh_cntr2', location is LC007, type is buried.
rfrsh_cntr2 = DFFE( _EQ004 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ004 = !fresh_cycle & _LC027;
-- Node name is ':49' = 'rfrsh_cntr3'
-- Equation name is 'rfrsh_cntr3', location is LC006, type is buried.
rfrsh_cntr3 = DFFE( _EQ005 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ005 = !fresh_cycle & _LC028;
-- Node name is ':48' = 'rfrsh_cntr4'
-- Equation name is 'rfrsh_cntr4', location is LC009, type is buried.
rfrsh_cntr4 = DFFE( _EQ006 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ006 = !fresh_cycle & _LC029;
-- Node name is ':47' = 'rfrsh_cntr5'
-- Equation name is 'rfrsh_cntr5', location is LC005, type is buried.
rfrsh_cntr5 = DFFE( _EQ007 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ007 = !fresh_cycle & _LC030;
-- Node name is ':46' = 'rfrsh_cntr6'
-- Equation name is 'rfrsh_cntr6', location is LC004, type is buried.
rfrsh_cntr6 = DFFE( _EQ008 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ008 = !fresh_cycle & _LC031;
-- Node name is ':45' = 'rfrsh_cntr7'
-- Equation name is 'rfrsh_cntr7', location is LC021, type is buried.
rfrsh_cntr7 = DFFE( _EQ009 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ009 = !fresh_cycle & _LC032;
-- Node name is ':44' = 'rfrsh_cntr8'
-- Equation name is 'rfrsh_cntr8', location is LC020, type is buried.
rfrsh_cntr8 = DFFE( _EQ010 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ010 = !fresh_cycle & _LC022;
-- Node name is ':43' = 'rfrsh_cntr9'
-- Equation name is 'rfrsh_cntr9', location is LC019, type is buried.
rfrsh_cntr9 = DFFE( _EQ011 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ011 = !fresh_cycle & _LC023;
-- Node name is ':42' = 'rfrsh_cntr10'
-- Equation name is 'rfrsh_cntr10', location is LC018, type is buried.
rfrsh_cntr10 = DFFE( _EQ012 $ GND, GLOBAL( clk), GLOBAL( rst_l), VCC, VCC);
_EQ012 = !fresh_cycle & _LC025;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL(!rfrsh_cntr1 $ !rfrsh_cntr0);
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( rfrsh_cntr2 $ _EQ013);
_EQ013 = rfrsh_cntr0 & rfrsh_cntr1;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( rfrsh_cntr3 $ _EQ014);
_EQ014 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( rfrsh_cntr4 $ _EQ015);
_EQ015 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( rfrsh_cntr5 $ _EQ016);
_EQ016 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( rfrsh_cntr6 $ _EQ017);
_EQ017 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( rfrsh_cntr7 $ _EQ018);
_EQ018 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( rfrsh_cntr8 $ _EQ019);
_EQ019 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & rfrsh_cntr7;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( rfrsh_cntr9 $ _EQ020);
_EQ020 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & rfrsh_cntr7 &
rfrsh_cntr8;
-- Node name is '|lpm_add_sub:73|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( rfrsh_cntr10 $ _EQ021);
_EQ021 = rfrsh_cntr0 & rfrsh_cntr1 & rfrsh_cntr2 & rfrsh_cntr3 &
rfrsh_cntr4 & rfrsh_cntr5 & rfrsh_cntr6 & rfrsh_cntr7 &
rfrsh_cntr8 & rfrsh_cntr9;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\newsdram\sd_rfrsh.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,445K
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