📄 sd_sig.rpt
字号:
135 - - - 18 OUTPUT 0 1 0 0 sd_dqm1
31 - - C -- OUTPUT 0 1 0 0 sd_dqm2
47 - - - 16 OUTPUT 0 1 0 0 sd_dqm3
26 - - C -- OUTPUT 0 1 0 0 sd_dqm4
44 - - - 18 OUTPUT 0 1 0 0 sd_dqm5
131 - - - 15 OUTPUT 0 1 0 0 sd_dqm6
132 - - - 16 OUTPUT 0 1 0 0 sd_dqm7
30 - - C -- OUTPUT 0 1 0 0 sd_dqm8
32 - - C -- OUTPUT 0 1 0 0 sd_dqm9
46 - - - 17 OUTPUT 0 1 0 0 sd_dqm10
88 - - B -- OUTPUT 0 1 0 0 sd_dqm11
43 - - - 18 OUTPUT 0 1 0 0 sd_dqm12
78 - - C -- OUTPUT 0 1 0 0 sd_dqm13
86 - - B -- OUTPUT 0 1 0 0 sd_dqm14
33 - - C -- OUTPUT 0 1 0 0 sd_dqm15
112 - - - 03 OUTPUT 0 1 0 0 sd_ras_l
72 - - - 04 OUTPUT 0 1 0 0 sd_we_l
118 - - - 07 OUTPUT 0 1 0 0 state_cntr0
19 - - B -- OUTPUT 0 1 0 0 state_cntr1
29 - - C -- OUTPUT 0 1 0 0 state_cntr2
92 - - B -- OUTPUT 0 1 0 0 state_cntr3
89 - - B -- OUTPUT 0 1 0 0 state_cntr4
67 - - - 08 OUTPUT 0 1 0 0 state_cntr5
68 - - - 07 OUTPUT 0 1 0 0 state_cntr6
119 - - - 08 OUTPUT 0 1 0 0 state_cntr7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 06 AND2 0 3 0 4 |lpm_add_sub:758|addcore:adder|:125
- 8 - A 01 AND2 0 3 0 1 |lpm_add_sub:758|addcore:adder|:133
- 4 - A 01 AND2 0 4 0 2 |lpm_add_sub:758|addcore:adder|:137
- 2 - B 07 DFFE + 1 1 1 0 :130
- 6 - B 07 DFFE + 1 1 1 1 :131
- 8 - B 07 DFFE + 1 1 1 1 :132
- 5 - B 07 DFFE + 1 1 1 1 :133
- 1 - B 07 DFFE + 1 1 1 2 :134
- 4 - B 07 DFFE + 1 1 1 1 :135
- 3 - B 07 DFFE + 1 1 1 1 :136
- 7 - B 07 DFFE + 1 0 1 9 :137
- 2 - B 03 OR2 ! 1 1 0 13 :138
- 8 - B 03 AND2 1 1 0 12 :236
- 7 - B 02 AND2 1 1 0 1 :241
- 8 - A 21 AND2 1 1 0 1 :242
- 6 - A 21 AND2 1 1 0 1 :243
- 2 - A 21 AND2 1 1 0 1 :244
- 1 - A 21 AND2 1 1 0 1 :245
- 6 - A 11 AND2 1 1 0 1 :246
- 5 - A 11 AND2 1 1 0 1 :247
- 2 - A 11 AND2 1 1 0 1 :248
- 3 - B 02 AND2 1 1 0 3 :250
- 2 - B 02 AND2 0 2 0 10 :366
- 4 - B 02 DFFE + ! 1 3 1 0 :414
- 4 - A 11 DFFE + 1 3 1 0 :415
- 8 - A 11 DFFE + 1 3 1 0 :416
- 5 - B 02 DFFE + 1 3 1 0 :417
- 4 - A 21 DFFE + 1 3 1 0 :418
- 5 - A 21 DFFE + 1 3 1 0 :419
- 7 - A 21 DFFE + 1 3 1 0 :420
- 3 - A 21 DFFE + 1 3 1 0 :421
- 3 - A 11 DFFE + 1 3 1 0 :422
- 7 - A 11 DFFE + 1 3 1 0 :423
- 1 - A 11 DFFE + 1 3 1 0 :424
- 6 - B 02 OR2 s 1 3 0 2 ~462~1
- 1 - B 02 DFFE + 1 2 1 0 :466
- 8 - B 02 DFFE + 1 2 1 0 :467
- 7 - B 03 DFFE + ! 4 0 1 0 :489
- 3 - B 03 DFFE + ! 2 2 1 0 :511
- 5 - A 03 DFFE + 1 1 0 9 op_en (:523)
- 4 - A 03 DFFE + 1 1 0 3 op_active (:529)
- 1 - A 03 AND2 0 2 0 8 :532
- 7 - A 01 OR2 0 4 0 1 :550
- 5 - A 01 OR2 0 3 0 1 :551
- 2 - A 08 OR2 0 3 0 1 :552
- 3 - A 01 OR2 0 4 0 1 :553
- 3 - A 03 OR2 0 3 0 1 :554
- 6 - A 06 OR2 0 4 0 1 :555
- 3 - A 06 OR2 0 3 0 1 :556
- 6 - A 01 DFFE + 1 2 0 2 op_num7 (:583)
- 2 - A 01 DFFE + 1 2 0 3 op_num6 (:584)
- 1 - A 08 DFFE + 1 2 0 3 op_num5 (:585)
- 1 - A 01 DFFE + 1 2 0 4 op_num4 (:586)
- 8 - A 03 DFFE + 1 2 0 5 op_num3 (:587)
- 7 - A 06 DFFE + 1 2 0 3 op_num2 (:588)
- 5 - A 06 DFFE + 1 2 0 4 op_num1 (:589)
- 2 - A 06 DFFE + 1 2 0 4 op_num0 (:590)
- 6 - A 08 OR2 ! 1 2 0 1 :604
- 5 - A 08 OR2 ! 1 2 0 1 :609
- 4 - A 08 OR2 ! 1 2 0 1 :614
- 3 - A 08 OR2 ! 1 2 0 1 :619
- 4 - A 06 OR2 ! 1 2 0 1 :624
- 8 - A 06 OR2 ! 2 2 0 1 :629
- 8 - A 08 OR2 s 1 2 0 1 ~637~1
- 7 - A 03 DFFE + 1 2 1 2 :643
- 6 - A 03 DFFE + 0 2 1 1 :647
- 2 - A 03 AND2 1 1 0 18 :648
- 1 - B 03 DFFE + ! 2 2 1 0 :661
- 4 - B 03 OR2 s ! 2 0 0 2 ~677~1
- 6 - B 03 DFFE + ! 1 3 1 0 :680
- 1 - C 19 DFFE + 0 0 1 0 :682
- 8 - C 18 DFFE + 2 1 1 0 :736
- 8 - C 15 DFFE + 2 1 1 0 :737
- 7 - C 15 DFFE + 2 1 1 0 :738
- 5 - C 18 DFFE + 2 1 1 0 :739
- 6 - C 15 DFFE + 2 1 1 0 :740
- 4 - C 18 DFFE + 2 1 1 0 :741
- 7 - C 18 DFFE + 2 1 1 0 :742
- 5 - C 15 DFFE + 2 1 1 0 :743
- 3 - C 15 DFFE + 2 1 1 0 :744
- 1 - C 15 DFFE + 2 1 1 0 :745
- 2 - C 18 DFFE + 2 1 1 0 :746
- 1 - C 18 DFFE + 2 1 1 0 :747
- 2 - C 15 DFFE + 2 1 1 0 :748
- 6 - C 18 DFFE + 2 1 1 0 :749
- 3 - C 18 DFFE + 2 1 1 0 :750
- 4 - C 15 DFFE + 2 1 1 0 :751
- 4 - B 11 DFFE + ! 1 0 1 0 :757
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 17/ 96( 17%) 22/ 48( 45%) 5/ 48( 10%) 10/16( 62%) 6/16( 37%) 0/16( 0%)
B: 11/ 96( 11%) 8/ 48( 16%) 0/ 48( 0%) 7/16( 43%) 7/16( 43%) 0/16( 0%)
C: 10/ 96( 10%) 1/ 48( 2%) 14/ 48( 29%) 6/16( 37%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 6/24( 25%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
13: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
23: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 55 clk
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 35 rst_l
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** EQUATIONS **
add4 : INPUT;
add5 : INPUT;
add6 : INPUT;
add7 : INPUT;
add8 : INPUT;
add9 : INPUT;
add10 : INPUT;
add11 : INPUT;
add12 : INPUT;
add13 : INPUT;
add14 : INPUT;
add15 : INPUT;
add16 : INPUT;
add17 : INPUT;
add18 : INPUT;
add19 : INPUT;
add20 : INPUT;
add21 : INPUT;
add22 : INPUT;
add23 : INPUT;
add24 : INPUT;
byte_en0 : INPUT;
byte_en1 : INPUT;
byte_en2 : INPUT;
byte_en3 : INPUT;
byte_en4 : INPUT;
byte_en5 : INPUT;
byte_en6 : INPUT;
byte_en7 : INPUT;
byte_en8 : INPUT;
byte_en9 : INPUT;
byte_en10 : INPUT;
byte_en11 : INPUT;
byte_en12 : INPUT;
byte_en13 : INPUT;
byte_en14 : INPUT;
byte_en15 : INPUT;
charge_cycle : INPUT;
ch_num0 : INPUT;
ch_num1 : INPUT;
ch_num2 : INPUT;
ch_num3 : INPUT;
ch_num4 : INPUT;
ch_num5 : INPUT;
ch_num6 : INPUT;
ch_num7 : INPUT;
clk : INPUT;
data_cycle : INPUT;
fresh_cycle : INPUT;
idle_cycle : INPUT;
load_cycle : INPUT;
rst_l : INPUT;
wr_l : INPUT;
-- Node name is 'ack_l'
-- Equation name is 'ack_l', type is output
ack_l = _LC4_B11;
-- Node name is ':529' = 'op_active'
-- Equation name is 'op_active', location is LC4_A3, type is buried.
op_active = DFFE( op_en, GLOBAL( clk), VCC, VCC, data_cycle);
-- Node name is ':523' = 'op_en'
-- Equation name is 'op_en', location is LC5_A3, type is buried.
op_en = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = data_cycle & _LC7_B7
# data_cycle & op_en;
-- Node name is ':590' = 'op_num0'
-- Equation name is 'op_num0', location is LC2_A6, type is buried.
op_num0 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ002 = !_LC1_A3 & op_en & op_num0
# _LC1_A3 & op_en & !op_num0;
-- Node name is ':589' = 'op_num1'
-- Equation name is 'op_num1', location is LC5_A6, type is buried.
op_num1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ003 = _LC3_A6 & op_en;
-- Node name is ':588' = 'op_num2'
-- Equation name is 'op_num2', location is LC7_A6, type is buried.
op_num2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ004 = _LC6_A6 & op_en;
-- Node name is ':587' = 'op_num3'
-- Equation name is 'op_num3', location is LC8_A3, type is buried.
op_num3 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ005 = _LC3_A3 & op_en;
-- Node name is ':586' = 'op_num4'
-- Equation name is 'op_num4', location is LC1_A1, type is buried.
op_num4 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ006 = _LC3_A1 & op_en;
-- Node name is ':585' = 'op_num5'
-- Equation name is 'op_num5', location is LC1_A8, type is buried.
op_num5 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ007 = _LC2_A8 & op_en;
-- Node name is ':584' = 'op_num6'
-- Equation name is 'op_num6', location is LC2_A1, type is buried.
op_num6 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ008 = _LC5_A1 & op_en;
-- Node name is ':583' = 'op_num7'
-- Equation name is 'op_num7', location is LC6_A1, type is buried.
op_num7 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, data_cycle);
_EQ009 = _LC7_A1 & op_en;
-- Node name is 'op_over'
-- Equation name is 'op_over', type is output
op_over = _LC7_A3;
-- Node name is 'rs_ready'
-- Equation name is 'rs_ready', type is output
rs_ready = _LC6_A3;
-- Node name is 'sd_add0'
-- Equation name is 'sd_add0', type is output
sd_add0 = _LC1_A11;
-- Node name is 'sd_add1'
-- Equation name is 'sd_add1', type is output
sd_add1 = _LC7_A11;
-- Node name is 'sd_add2'
-- Equation name is 'sd_add2', type is output
sd_add2 = _LC3_A11;
-- Node name is 'sd_add3'
-- Equation name is 'sd_add3', type is output
sd_add3 = _LC3_A21;
-- Node name is 'sd_add4'
-- Equation name is 'sd_add4', type is output
sd_add4 = _LC7_A21;
-- Node name is 'sd_add5'
-- Equation name is 'sd_add5', type is output
sd_add5 = _LC5_A21;
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