📄 sd_sig.rpt
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Project Information d:\newsdram\sd_sig.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/24/2008 16:52:26
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
sd_sig EPF10K10TC144-3 53 46 0 0 0 % 88 15 %
User Pins: 53 46 0
Project Information d:\newsdram\sd_sig.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop ':413' stuck at GND
Warning: Ignored unnecessary INPUT pin 'add3'
Warning: Ignored unnecessary INPUT pin 'add2'
Warning: Ignored unnecessary INPUT pin 'add1'
Warning: Ignored unnecessary INPUT pin 'add0'
Warning: Ignored unnecessary INPUT pin 'term_l'
Project Information d:\newsdram\sd_sig.rpt
** FILE HIERARCHY **
|lpm_add_sub:758|
|lpm_add_sub:758|addcore:adder|
|lpm_add_sub:758|altshift:result_ext_latency_ffs|
|lpm_add_sub:758|altshift:carry_ext_latency_ffs|
|lpm_add_sub:758|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
***** Logic for device 'sd_sig' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** ERROR SUMMARY **
Info: Chip 'sd_sig' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
c
h s s
a t t i
b b r a a d
y b b y b b g t t l s
t y y s t s y s s y e c c c e e c e d s
e t t d e s d t d d t G _ h V h h _ _ h _ _ s d
_ e e _ _ G a d _ V e _ _ e G a N c _ C a _ _ c c V _ c r d _ a
e _ _ a e N d _ a d C _ d d _ N d D y n w C c n n n n a a C n y a _ a d
n e e d n D d c d q C e q q e D d I c u r I k u u t t d d C u c s b d d
1 n n d 1 I 1 k d m I n m m n I 1 N l m _ N _ m m r r d d I m l _ a d 1
0 0 6 6 2 O 7 e 8 1 O 5 7 6 3 O 6 T e 7 l T l 1 3 7 0 5 6 O 0 e l 0 7 2
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
ch_num5 | 7 102 | add20
add9 | 8 101 | add13
ch_num4 | 9 100 | ch_num6
add7 | 10 99 | sd_add9
sd_add5 | 11 98 | ch_num2
add10 | 12 97 | rs_ready
sd_add4 | 13 96 | op_over
add15 | 14 95 | sd_add8
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
fresh_cycle | 17 92 | state_cntr3
add11 | 18 91 | add22
state_cntr1 | 19 EPF10K10TC144-3 90 | sd_add10
add23 | 20 89 | state_cntr4
add19 | 21 88 | sd_dqm11
load_cycle | 22 87 | sd_cs0_l
add24 | 23 86 | sd_dqm14
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
sd_dqm4 | 26 83 | sd_cas_l
byte_en4 | 27 82 | byte_en9
byte_en15 | 28 81 | byte_en11
state_cntr2 | 29 80 | byte_en7
sd_dqm8 | 30 79 | byte_en1
sd_dqm2 | 31 78 | sd_dqm13
sd_dqm9 | 32 77 | ^MSEL0
sd_dqm15 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
add18 | 36 73 | sd_ba1
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
b s b G b R s s V s s s R G b V V r c d G G s s V s s a a G s s R a V s
y d y N y E d d C d d d E N y C C s l a N N d d C d d d d N t t E d C d
t _ t D t S _ _ C _ _ _ S D t C C t k t D D _ _ C _ _ d d D a a S d C _
e a e I e E d d I d d d E I e I I _ a I I a a I a a 4 2 I t t E 1 I w
_ d _ O _ R q q O q q q R O _ N N l _ N N d d O d d 1 O e e R 4 O e
e d e e V m m m m m V e T T c T T d d d d _ _ V _
n 3 n n E 1 5 1 3 0 E n y 1 2 1 0 c c E l
8 1 1 D 2 0 D 2 c 1 n n D
3 4 l t t
e r r
5 6
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A3 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
A6 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
A8 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 14/22( 63%)
A11 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
A21 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 11/22( 50%)
B2 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 1/2 1/2 11/22( 50%)
B3 7/ 8( 87%) 5/ 8( 62%) 3/ 8( 37%) 1/2 1/2 7/22( 31%)
B7 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
B11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 1/22( 4%)
C15 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 1/2 1/2 10/22( 45%)
C18 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
C19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 93/96 ( 96%)
Total logic cells used: 88/576 ( 15%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.90/4 ( 72%)
Total fan-in: 256/2304 ( 11%)
Total input pins required: 53
Total input I/O cell registers required: 0
Total output pins required: 46
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 88
Total flipflops required: 55
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 3/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 8 0 0 8 0 7 0 0 8 0 0 0 0 0 0 0 0 0 0 8 0 0 0 47/0
B: 0 8 7 0 0 0 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 1 0 0 0 0 0 17/0
Total: 8 8 15 0 0 8 8 7 0 0 9 0 0 0 0 8 0 0 8 1 0 8 0 0 0 88/0
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
64 - - - 10 INPUT 0 0 0 1 add4
117 - - - 06 INPUT 0 0 0 1 add5
116 - - - 05 INPUT 0 0 0 1 add6
10 - - A -- INPUT 0 0 0 1 add7
136 - - - 19 INPUT 0 0 0 1 add8
8 - - A -- INPUT 0 0 0 1 add9
12 - - A -- INPUT 0 0 0 1 add10
18 - - B -- INPUT 0 0 0 1 add11
109 - - - 01 INPUT 0 0 0 1 add12
101 - - A -- INPUT 0 0 0 1 add13
70 - - - 05 INPUT 0 0 0 1 add14
14 - - A -- INPUT 0 0 0 1 add15
128 - - - 13 INPUT 0 0 0 1 add16
138 - - - 20 INPUT 0 0 0 1 add17
36 - - - 24 INPUT 0 0 0 1 add18
21 - - B -- INPUT 0 0 0 1 add19
102 - - A -- INPUT 0 0 0 1 add20
65 - - - 09 INPUT 0 0 0 1 add21
91 - - B -- INPUT 0 0 0 1 add22
20 - - B -- INPUT 0 0 0 1 add23
23 - - B -- INPUT 0 0 0 1 add24
143 - - - 24 INPUT 0 0 0 1 byte_en0
79 - - C -- INPUT 0 0 0 1 byte_en1
51 - - - 13 INPUT 0 0 0 1 byte_en2
130 - - - 14 INPUT 0 0 0 1 byte_en3
27 - - C -- INPUT 0 0 0 1 byte_en4
133 - - - 17 INPUT 0 0 0 1 byte_en5
142 - - - 23 INPUT 0 0 0 1 byte_en6
80 - - C -- INPUT 0 0 0 1 byte_en7
37 - - - 23 INPUT 0 0 0 1 byte_en8
82 - - C -- INPUT 0 0 0 1 byte_en9
144 - - - 24 INPUT 0 0 0 1 byte_en10
81 - - C -- INPUT 0 0 0 1 byte_en11
140 - - - 21 INPUT 0 0 0 1 byte_en12
39 - - - 21 INPUT 0 0 0 1 byte_en13
41 - - - 20 INPUT 0 0 0 1 byte_en14
28 - - C -- INPUT 0 0 0 1 byte_en15
126 - - - -- INPUT 0 0 0 3 charge_cycle
114 - - - 04 INPUT 0 0 0 1 ch_num0
121 - - - 10 INPUT 0 0 0 1 ch_num1
98 - - A -- INPUT 0 0 0 1 ch_num2
120 - - - 09 INPUT 0 0 0 1 ch_num3
9 - - A -- INPUT 0 0 0 1 ch_num4
7 - - A -- INPUT 0 0 0 1 ch_num5
100 - - A -- INPUT 0 0 0 1 ch_num6
125 - - - -- INPUT 0 0 0 1 ch_num7
55 - - - -- INPUT G 0 0 0 0 clk
56 - - - -- INPUT 0 0 0 17 data_cycle
17 - - B -- INPUT 0 0 0 3 fresh_cycle
113 - - - 03 INPUT 0 0 0 8 idle_cycle
22 - - B -- INPUT 0 0 0 4 load_cycle
54 - - - -- INPUT G 0 0 0 0 rst_l
124 - - - -- INPUT 0 0 0 17 wr_l
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\newsdram\sd_sig.rpt
sd_sig
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - - 12 OUTPUT 0 1 0 0 ack_l
96 - - A -- OUTPUT 0 1 0 0 op_over
97 - - A -- OUTPUT 0 1 0 0 rs_ready
63 - - - 11 OUTPUT 0 1 0 0 sd_add0
62 - - - 11 OUTPUT 0 1 0 0 sd_add1
60 - - - 12 OUTPUT 0 1 0 0 sd_add2
38 - - - 22 OUTPUT 0 1 0 0 sd_add3
13 - - A -- OUTPUT 0 1 0 0 sd_add4
11 - - A -- OUTPUT 0 1 0 0 sd_add5
141 - - - 22 OUTPUT 0 1 0 0 sd_add6
110 - - - 01 OUTPUT 0 1 0 0 sd_add7
95 - - A -- OUTPUT 0 1 0 0 sd_add8
99 - - A -- OUTPUT 0 1 0 0 sd_add9
90 - - B -- OUTPUT 0 1 0 0 sd_add10
59 - - - 12 OUTPUT 0 0 0 0 sd_add11
111 - - - 02 OUTPUT 0 1 0 0 sd_ba0
73 - - - 02 OUTPUT 0 1 0 0 sd_ba1
83 - - C -- OUTPUT 0 1 0 0 sd_cas_l
137 - - - 19 OUTPUT 0 1 0 0 sd_cke
87 - - B -- OUTPUT 0 1 0 0 sd_cs0_l
48 - - - 15 OUTPUT 0 1 0 0 sd_dqm0
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