wr_sel_pipe.v

8读8写SDRAM verilog 程序

////
`timescale 1 ns /  100 ps
module wr_sel_pipe(
			clk,w0sel,w1sel,w2sel,
			wda,wdb,wdc,wdd,wde,wdf,wdg,wdh,
			wma,wmb,wmc,wmd,wme,wmf,wmg,wmh,
			w2buf,
			wdqm
			);
input	clk;
input	[3:0]	w0sel;
input	[1:0]	w1sel;
input			w2sel;
input	[127:0]	wda,wdb,wdc,wdd,wde,wdf,wdg,wdh;
input	[15:0]	wma,wmb,wmc,wmd,wme,wmf,wmg,wmh;
output	[127:0]	w2buf;
output	[15:0]	wdqm;

//source select pipe0
reg [127:0]		w0bufa,w0bufb,w0bufc,w0bufd;
reg [15:0]		w0ma,w0mb,w0mc,w0md;
always @(posedge clk) begin
	if(w0sel[0])begin
		w0bufa<= #1  wda;
		w0ma<= #1  wma;
	end
	else begin
		w0bufa<= #1  wdb;
		w0ma<= #1  wmb;
	end		
		
	if(w0sel[1])begin
		w0bufb<= #1  wdc;
		w0mb<= #1  wmc;
	end
	else begin
		w0bufb<= #1  wdd;
		w0mb<= #1  wmd;
	end
		
	if(w0sel[2])begin
		w0bufc<= #1  wde;
		w0mc<= #1  wme;
	end
	else begin
		w0bufc<= #1  wdf;
		w0mc<= #1  wmf;
	end
		
	if(w0sel[3]) begin
		w0bufd<= #1  wdg;
		w0md<= #1  wmg;
	end
	else begin
		w0bufd<= #1  wdh;
		w0md<= #1  wmh;
	end
end
//source select pipe1
//wire [1:0]	w1sel;
reg [127:0]	w1bufa,w1bufb;	
reg [15:0]	w1ma,w1mb;
always @(posedge clk)begin
	if(w1sel[0])begin
		w1bufa<= #1  w0bufa;
		w1ma<= #1  w0ma;
	end
	else begin
		w1bufa<= #1  w0bufb;
		w1ma<= #1  w0mb;
	end
	if(w1sel[1])begin
		w1bufb<= #1  w0bufc;
		w1mb<= #1  w0mc;
	end
	else begin
		w1bufb<= #1  w0bufd;
		w1mb<= #1  w0md;
	end
end
//source select pipe2
//reg 	w2sel;

reg [127:0]	w2buf;	
//reg [15:0]	wdqm;
always @(posedge clk)begin
	if(w2sel)begin
		w2buf<= #1  w1bufa;
		//wdqm<= #1  w1ma;
	end
	else begin
		w2buf<= #1  w1bufb;
		//wdqm<= #1  w1mb;
	end
end
/*
wire[127:0]	w2buf;
assign	w2buf=w2sel ? w1bufa : w1bufb;
*/
assign wdqm=w2sel ? w1ma : w1mb;
endmodule