📄 sd_if.rpt
字号:
- 5 - B 22 DFFE + ! 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:517
- 5 - B 17 AND2 s 0 2 0 5 |sd_top:sd_top1|sd_sig:u4|~533~1
- 3 - B 20 DFFE + ! 1 3 1 0 |sd_top:sd_top1|sd_sig:u4|:536
- 5 - C 05 DFFE + 0 0 1 0 |sd_top:sd_top1|sd_sig:u4|:538
- 6 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:592
- 7 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:593
- 7 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:594
- 5 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:595
- 8 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:596
- 1 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:597
- 2 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:598
- 3 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:599
- 5 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:600
- 4 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:601
- 8 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:602
- 4 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:603
- 1 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:604
- 6 - A 02 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:605
- 2 - B 20 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:606
- 4 - A 04 DFFE + 2 1 1 0 |sd_top:sd_top1|sd_sig:u4|:607
- 2 - B 23 AND2 0 4 0 5 |sd_top:sd_top1|sd_state:u2|:20
- 1 - B 23 AND2 0 4 0 4 |sd_top:sd_top1|sd_state:u2|:26
- 3 - B 21 OR2 ! 0 4 0 2 |sd_top:sd_top1|sd_state:u2|:38
- 5 - B 21 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_state:u2|charge_on (|sd_top:sd_top1|sd_state:u2|:50)
- 4 - B 21 OR2 0 2 0 4 |sd_top:sd_top1|sd_state:u2|:51
- 4 - B 17 OR2 s ! 0 4 0 2 |sd_top:sd_top1|sd_state:u2|~120~1
- 3 - B 17 AND2 s 0 3 0 1 |sd_top:sd_top1|sd_state:u2|~120~2
- 7 - B 17 AND2 0 4 0 1 |sd_top:sd_top1|sd_state:u2|:121
- 3 - B 23 OR2 s 0 2 0 4 |sd_top:sd_top1|sd_state:u2|~190~1
- 2 - B 17 AND2 0 4 0 1 |sd_top:sd_top1|sd_state:u2|:213
- 6 - B 21 OR2 s ! 0 4 0 1 |sd_top:sd_top1|sd_state:u2|~231~1
- 7 - B 21 OR2 s 0 4 0 1 |sd_top:sd_top1|sd_state:u2|~231~2
- 1 - B 21 DFFE + 0 4 0 8 |sd_top:sd_top1|sd_state:u2|sdram_cycle4 (|sd_top:sd_top1|sd_state:u2|:233)
- 6 - B 17 DFFE + 0 4 0 25 |sd_top:sd_top1|sd_state:u2|sdram_cycle3 (|sd_top:sd_top1|sd_state:u2|:234)
- 1 - B 13 DFFE + 1 3 0 28 |sd_top:sd_top1|sd_state:u2|sdram_cycle2 (|sd_top:sd_top1|sd_state:u2|:235)
- 1 - B 17 DFFE + 0 4 0 23 |sd_top:sd_top1|sd_state:u2|sdram_cycle1 (|sd_top:sd_top1|sd_state:u2|:236)
- 8 - B 21 DFFE + ! 0 4 0 7 |sd_top:sd_top1|sd_state:u2|sdram_cycle0 (|sd_top:sd_top1|sd_state:u2|:237)
- 6 - B 05 AND2 ! 0 2 0 3 |sd_top:sd_top1|:93
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 12/ 48( 25%) 6/ 48( 12%) 1/16( 6%) 11/16( 68%) 0/16( 0%)
B: 52/ 96( 54%) 8/ 48( 16%) 10/ 48( 20%) 5/16( 31%) 6/16( 37%) 0/16( 0%)
C: 30/ 96( 31%) 1/ 48( 2%) 16/ 48( 33%) 6/16( 37%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
13: 4/24( 16%) 0/4( 0%) 4/4(100%) 0/4( 0%)
14: 7/24( 29%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
15: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
16: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
17: 4/24( 16%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
18: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
19: 4/24( 16%) 2/4( 50%) 2/4( 50%) 0/4( 0%)
20: 4/24( 16%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
21: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
22: 6/24( 25%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 5/24( 20%) 3/4( 75%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 112 clk
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 62 rst_l
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** EQUATIONS **
ch_addr0 : INPUT;
ch_addr1 : INPUT;
ch_addr2 : INPUT;
ch_addr3 : INPUT;
ch_addr4 : INPUT;
ch_addr5 : INPUT;
ch_addr6 : INPUT;
ch_addr7 : INPUT;
ch_addr8 : INPUT;
ch_addr9 : INPUT;
ch_addr10 : INPUT;
ch_addr11 : INPUT;
ch_addr12 : INPUT;
ch_addr13 : INPUT;
ch_addr14 : INPUT;
ch_addr15 : INPUT;
ch_addr16 : INPUT;
ch_addr17 : INPUT;
ch_addr18 : INPUT;
ch_addr19 : INPUT;
ch_addr20 : INPUT;
ch_dqm0 : INPUT;
ch_dqm1 : INPUT;
ch_dqm2 : INPUT;
ch_dqm3 : INPUT;
ch_dqm4 : INPUT;
ch_dqm5 : INPUT;
ch_dqm6 : INPUT;
ch_dqm7 : INPUT;
ch_dqm8 : INPUT;
ch_dqm9 : INPUT;
ch_dqm10 : INPUT;
ch_dqm11 : INPUT;
ch_dqm12 : INPUT;
ch_dqm13 : INPUT;
ch_dqm14 : INPUT;
ch_dqm15 : INPUT;
ch_num0 : INPUT;
ch_num1 : INPUT;
ch_num2 : INPUT;
ch_num3 : INPUT;
ch_num4 : INPUT;
ch_num5 : INPUT;
ch_num6 : INPUT;
ch_num7 : INPUT;
ch_req : INPUT;
ch_rw : INPUT;
clk : INPUT;
rst_l : INPUT;
sdram_en : INPUT;
-- Node name is 'ch_ack'
-- Equation name is 'ch_ack', type is output
ch_ack = _LC5_B13;
-- Node name is 'dp_addr0'
-- Equation name is 'dp_addr0', type is output
dp_addr0 = _LC8_A22;
-- Node name is 'dp_addr1'
-- Equation name is 'dp_addr1', type is output
dp_addr1 = _LC6_A22;
-- Node name is 'dp_addr2'
-- Equation name is 'dp_addr2', type is output
dp_addr2 = _LC4_A14;
-- Node name is 'dp_addr3'
-- Equation name is 'dp_addr3', type is output
dp_addr3 = _LC8_A14;
-- Node name is 'dp_addr4'
-- Equation name is 'dp_addr4', type is output
dp_addr4 = _LC2_A14;
-- Node name is 'dp_addr5'
-- Equation name is 'dp_addr5', type is output
dp_addr5 = _LC5_A14;
-- Node name is 'dp_addr6'
-- Equation name is 'dp_addr6', type is output
dp_addr6 = _LC3_A14;
-- Node name is 'dp_addr7'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -