📄 sd_if.rpt
字号:
104 - - - 01 OUTPUT 0 1 0 0 sd_dqm6
143 - - A -- OUTPUT 0 1 0 0 sd_dqm7
148 - - A -- OUTPUT 0 1 0 0 sd_dqm8
157 - - - 01 OUTPUT 0 1 0 0 sd_dqm9
159 - - - 02 OUTPUT 0 1 0 0 sd_dqm10
198 - - - 19 OUTPUT 0 1 0 0 sd_dqm11
28 - - B -- OUTPUT 0 1 0 0 sd_dqm12
61 - - - 20 OUTPUT 0 1 0 0 sd_dqm13
141 - - A -- OUTPUT 0 1 0 0 sd_dqm14
30 - - B -- OUTPUT 0 1 0 0 sd_dqm15
136 - - B -- OUTPUT 0 1 0 0 sdram_setup
205 - - - 23 OUTPUT 0 1 0 0 sd_ras_l
199 - - - 20 OUTPUT 0 1 0 0 sd_we_l
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 02 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:410|addcore:adder|:121
- 4 - B 02 AND2 0 3 0 1 |rw_sd_mach:u1|lpm_add_sub:410|addcore:adder|:125
- 8 - B 02 AND2 0 4 0 4 |rw_sd_mach:u1|lpm_add_sub:410|addcore:adder|:129
- 4 - B 06 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:410|addcore:adder|:133
- 2 - B 12 AND2 0 3 0 1 |rw_sd_mach:u1|lpm_add_sub:410|addcore:adder|:137
- 4 - B 12 AND2 0 4 0 1 |rw_sd_mach:u1|lpm_add_sub:410|addcore:adder|:141
- 1 - A 22 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:411|addcore:adder|:121
- 1 - A 14 AND2 0 4 0 3 |rw_sd_mach:u1|lpm_add_sub:411|addcore:adder|:129
- 7 - A 14 AND2 0 3 0 2 |rw_sd_mach:u1|lpm_add_sub:411|addcore:adder|:137
- 7 - C 20 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:155
- 2 - C 20 AND2 0 3 0 2 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:159
- 2 - C 23 AND2 0 2 0 2 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:163
- 1 - C 23 AND2 0 2 0 2 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:167
- 1 - C 15 AND2 0 2 0 2 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:171
- 2 - C 15 AND2 0 2 0 4 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:175
- 5 - C 18 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:179
- 6 - C 18 AND2 0 3 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:183
- 2 - C 18 AND2 0 4 0 4 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:187
- 6 - C 13 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:191
- 3 - C 13 AND2 0 3 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:195
- 4 - C 13 AND2 0 4 0 4 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:199
- 4 - C 14 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:203
- 2 - C 17 AND2 0 3 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:207
- 1 - C 17 AND2 0 4 0 2 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:211
- 8 - C 17 AND2 0 2 0 4 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:215
- 5 - C 21 AND2 0 2 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:219
- 7 - C 21 AND2 0 3 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:223
- 8 - C 21 AND2 0 4 0 1 |rw_sd_mach:u1|lpm_add_sub:412|addcore:adder|:227
- 6 - B 13 DFFE + 0 1 0 2 |rw_sd_mach:u1|op_en (|rw_sd_mach:u1|:91)
- 8 - B 13 AND2 0 2 0 8 |rw_sd_mach:u1|:96
- 7 - B 13 DFFE + 0 2 0 3 |rw_sd_mach:u1|op_active (|rw_sd_mach:u1|:100)
- 4 - B 13 OR2 ! 0 2 0 8 |rw_sd_mach:u1|:102
- 5 - B 12 DFFE + 0 3 0 1 |rw_sd_mach:u1|op_num7 (|rw_sd_mach:u1|:176)
- 3 - B 12 DFFE + 0 3 0 2 |rw_sd_mach:u1|op_num6 (|rw_sd_mach:u1|:177)
- 2 - B 06 DFFE + 0 3 0 3 |rw_sd_mach:u1|op_num5 (|rw_sd_mach:u1|:178)
- 3 - B 06 DFFE + 0 3 0 4 |rw_sd_mach:u1|op_num4 (|rw_sd_mach:u1|:179)
- 5 - B 02 DFFE + 0 3 0 2 |rw_sd_mach:u1|op_num3 (|rw_sd_mach:u1|:180)
- 3 - B 02 DFFE + 0 3 0 3 |rw_sd_mach:u1|op_num2 (|rw_sd_mach:u1|:181)
- 8 - B 06 DFFE + 0 3 0 4 |rw_sd_mach:u1|op_num1 (|rw_sd_mach:u1|:182)
- 1 - B 06 DFFE + 0 2 0 5 |rw_sd_mach:u1|op_num0 (|rw_sd_mach:u1|:183)
- 8 - B 12 OR2 ! 1 2 0 1 |rw_sd_mach:u1|:189
- 7 - B 12 OR2 ! 1 2 0 1 |rw_sd_mach:u1|:194
- 6 - B 12 OR2 ! 1 2 0 1 |rw_sd_mach:u1|:199
- 2 - B 02 OR2 ! 1 2 0 1 |rw_sd_mach:u1|:204
- 7 - B 02 OR2 ! 1 2 0 1 |rw_sd_mach:u1|:209
- 6 - B 02 OR2 ! 2 2 0 1 |rw_sd_mach:u1|:214
- 1 - B 12 OR2 s 1 2 0 1 |rw_sd_mach:u1|~222~1
- 5 - B 13 DFFE + 0 3 1 2 |rw_sd_mach:u1|op_over (|rw_sd_mach:u1|:228)
- 2 - A 24 AND2 1 1 1 0 |rw_sd_mach:u1|:231
- 2 - B 13 DFFE + 0 2 1 23 |rw_sd_mach:u1|:236
- 2 - C 22 AND2 0 2 0 28 |rw_sd_mach:u1|:244
- 8 - A 24 DFFE + 0 2 0 1 |rw_sd_mach:u1|rs_ready_delay4 (|rw_sd_mach:u1|:265)
- 7 - A 24 DFFE + 0 2 0 1 |rw_sd_mach:u1|rs_ready_delay3 (|rw_sd_mach:u1|:266)
- 5 - A 24 DFFE + 0 2 0 1 |rw_sd_mach:u1|rs_ready_delay2 (|rw_sd_mach:u1|:267)
- 4 - A 24 DFFE + 0 2 0 1 |rw_sd_mach:u1|rs_ready_delay1 (|rw_sd_mach:u1|:268)
- 3 - A 24 DFFE + 0 1 0 1 |rw_sd_mach:u1|rs_ready_delay0 (|rw_sd_mach:u1|:269)
- 6 - A 24 AND2 1 1 1 1 |rw_sd_mach:u1|:270
- 1 - A 24 OR2 1 2 0 8 |rw_sd_mach:u1|:272
- 6 - A 14 DFFE + 0 3 1 0 |rw_sd_mach:u1|:298
- 3 - A 14 DFFE + 0 2 1 1 |rw_sd_mach:u1|:299
- 5 - A 14 DFFE + 0 3 1 1 |rw_sd_mach:u1|:300
- 2 - A 14 DFFE + 0 2 1 2 |rw_sd_mach:u1|:301
- 8 - A 14 DFFE + 0 3 1 1 |rw_sd_mach:u1|:302
- 4 - A 14 DFFE + 0 3 1 2 |rw_sd_mach:u1|:303
- 6 - A 22 DFFE + 0 2 1 3 |rw_sd_mach:u1|:304
- 8 - A 22 DFFE + 0 1 1 4 |rw_sd_mach:u1|:305
- 3 - B 13 OR2 ! 1 1 0 2 |rw_sd_mach:u1|:306
- 2 - C 21 DFFE + 1 2 0 1 |rw_sd_mach:u1|:384
- 3 - C 21 DFFE + 1 2 0 2 |rw_sd_mach:u1|:385
- 4 - C 21 DFFE + 1 2 0 3 |rw_sd_mach:u1|:386
- 6 - C 21 DFFE + 1 2 0 4 |rw_sd_mach:u1|:387
- 5 - C 17 DFFE + 1 2 0 2 |rw_sd_mach:u1|:388
- 4 - C 17 DFFE + 1 2 0 2 |rw_sd_mach:u1|:389
- 5 - C 14 DFFE + 1 2 0 3 |rw_sd_mach:u1|:390
- 6 - C 14 DFFE + 1 2 0 4 |rw_sd_mach:u1|:391
- 5 - C 13 DFFE + 1 2 0 2 |rw_sd_mach:u1|:392
- 8 - C 13 DFFE + 1 2 0 3 |rw_sd_mach:u1|:393
- 7 - C 13 DFFE + 1 2 0 4 |rw_sd_mach:u1|:394
- 7 - C 18 DFFE + 1 2 0 2 |rw_sd_mach:u1|:395
- 4 - C 18 DFFE + 1 2 0 3 |rw_sd_mach:u1|:396
- 8 - C 18 DFFE + 1 2 0 4 |rw_sd_mach:u1|:397
- 4 - C 15 DFFE + 1 2 0 2 |rw_sd_mach:u1|:398
- 5 - C 15 DFFE + 1 2 0 2 |rw_sd_mach:u1|:399
- 4 - C 23 DFFE + 1 2 0 2 |rw_sd_mach:u1|:400
- 3 - C 23 DFFE + 1 2 0 2 |rw_sd_mach:u1|:401
- 3 - C 20 DFFE + 1 2 0 2 |rw_sd_mach:u1|:402
- 5 - C 20 DFFE + 1 2 0 3 |rw_sd_mach:u1|:403
- 4 - C 20 DFFE + 1 1 0 4 |rw_sd_mach:u1|:404
- 6 - B 04 AND2 0 4 0 5 |sd_top:sd_top1|sd_cnfg:u1|:11
- 1 - B 11 DFFE + 1 0 0 1 |sd_top:sd_top1|sd_cnfg:u1|sdram_en1 (|sd_top:sd_top1|sd_cnfg:u1|:17)
- 2 - B 11 DFFE + 0 1 0 5 |sd_top:sd_top1|sd_cnfg:u1|sdram_en2 (|sd_top:sd_top1|sd_cnfg:u1|:19)
- 5 - B 10 AND2 0 2 0 1 |sd_top:sd_top1|sd_cnfg:u1|:36
- 7 - B 04 AND2 0 4 0 5 |sd_top:sd_top1|sd_cnfg:u1|:37
- 3 - B 04 AND2 0 4 0 6 |sd_top:sd_top1|sd_cnfg:u1|:59
- 2 - B 04 AND2 0 4 0 3 |sd_top:sd_top1|sd_cnfg:u1|:81
- 8 - B 04 AND2 0 4 0 5 |sd_top:sd_top1|sd_cnfg:u1|:104
- 4 - B 04 AND2 0 4 0 6 |sd_top:sd_top1|sd_cnfg:u1|:126
- 5 - B 04 AND2 0 4 0 2 |sd_top:sd_top1|sd_cnfg:u1|:148
- 2 - B 05 OR2 s 0 3 0 1 |sd_top:sd_top1|sd_cnfg:u1|~170~1
- 7 - B 10 OR2 s 0 3 0 1 |sd_top:sd_top1|sd_cnfg:u1|~171~1
- 8 - B 10 OR2 s 0 3 0 2 |sd_top:sd_top1|sd_cnfg:u1|~171~2
- 1 - B 04 DFFE + 0 3 0 7 |sd_top:sd_top1|sd_cnfg:u1|state3 (|sd_top:sd_top1|sd_cnfg:u1|:173)
- 1 - B 10 DFFE + 0 4 0 7 |sd_top:sd_top1|sd_cnfg:u1|state2 (|sd_top:sd_top1|sd_cnfg:u1|:174)
- 4 - B 22 DFFE + 0 4 0 7 |sd_top:sd_top1|sd_cnfg:u1|state1 (|sd_top:sd_top1|sd_cnfg:u1|:175)
- 3 - B 10 DFFE + 0 4 0 7 |sd_top:sd_top1|sd_cnfg:u1|state0 (|sd_top:sd_top1|sd_cnfg:u1|:176)
- 1 - B 22 AND2 0 2 0 1 |sd_top:sd_top1|sd_cnfg:u1|:186
- 4 - B 10 OR2 s 0 3 0 1 |sd_top:sd_top1|sd_cnfg:u1|~190~1
- 6 - B 10 DFFE + 0 3 0 2 |sd_top:sd_top1|sd_cnfg:u1|:192
- 2 - B 10 OR2 s 0 3 0 1 |sd_top:sd_top1|sd_cnfg:u1|~206~1
- 2 - B 21 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_cnfg:u1|:208
- 3 - B 05 OR2 s 0 4 0 1 |sd_top:sd_top1|sd_cnfg:u1|~228~1
- 4 - B 05 OR2 s 0 2 0 1 |sd_top:sd_top1|sd_cnfg:u1|~228~2
- 5 - B 05 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_cnfg:u1|:230
- 7 - B 05 OR2 s 0 4 0 1 |sd_top:sd_top1|sd_cnfg:u1|~250~1
- 8 - B 05 OR2 s 0 4 0 1 |sd_top:sd_top1|sd_cnfg:u1|~250~2
- 1 - B 05 DFFE + 1 2 1 2 |sd_top:sd_top1|sd_cnfg:u1|:252
- 8 - B 07 AND2 0 2 0 1 |sd_top:sd_top1|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:83
- 4 - B 03 AND2 0 4 0 3 |sd_top:sd_top1|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:91
- 7 - B 03 AND2 0 3 0 2 |sd_top:sd_top1|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:99
- 2 - B 03 AND2 0 2 0 5 |sd_top:sd_top1|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:103
- 4 - B 01 AND2 0 2 0 1 |sd_top:sd_top1|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:107
- 1 - B 01 AND2 0 3 0 1 |sd_top:sd_top1|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:111
- 3 - B 01 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr10 (|sd_top:sd_top1|sd_rfrsh:u3|:42)
- 5 - B 01 DFFE + 0 3 0 2 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr9 (|sd_top:sd_top1|sd_rfrsh:u3|:43)
- 6 - B 01 DFFE + 0 3 0 3 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr8 (|sd_top:sd_top1|sd_rfrsh:u3|:44)
- 7 - B 01 DFFE + 0 2 0 4 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr7 (|sd_top:sd_top1|sd_rfrsh:u3|:45)
- 8 - B 03 DFFE + 0 2 0 1 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr6 (|sd_top:sd_top1|sd_rfrsh:u3|:46)
- 6 - B 03 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr5 (|sd_top:sd_top1|sd_rfrsh:u3|:47)
- 5 - B 03 DFFE + 0 2 0 2 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr4 (|sd_top:sd_top1|sd_rfrsh:u3|:48)
- 3 - B 03 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr3 (|sd_top:sd_top1|sd_rfrsh:u3|:49)
- 1 - B 03 DFFE + 0 3 0 2 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr2 (|sd_top:sd_top1|sd_rfrsh:u3|:50)
- 1 - B 07 DFFE + 0 2 0 3 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr1 (|sd_top:sd_top1|sd_rfrsh:u3|:51)
- 2 - B 07 DFFE + 0 1 0 4 |sd_top:sd_top1|sd_rfrsh:u3|rfrsh_cntr0 (|sd_top:sd_top1|sd_rfrsh:u3|:52)
- 8 - B 01 AND2 s 0 4 0 1 |sd_top:sd_top1|sd_rfrsh:u3|~53~1
- 2 - B 01 DFFE + 0 3 0 1 |sd_top:sd_top1|sd_rfrsh:u3|:72
- 5 - B 23 DFFE + 0 2 0 4 |sd_top:sd_top1|sd_sig:u4|:123
- 8 - B 23 DFFE + 0 2 0 1 |sd_top:sd_top1|sd_sig:u4|:124
- 7 - B 23 DFFE + 0 2 0 1 |sd_top:sd_top1|sd_sig:u4|:125
- 4 - B 23 DFFE + 0 1 0 33 |sd_top:sd_top1|sd_sig:u4|:126
- 7 - C 17 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:230
- 7 - C 15 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:231
- 1 - C 13 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:234
- 7 - B 22 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:235
- 3 - C 18 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:236
- 1 - C 16 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:237
- 1 - C 18 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:357
- 6 - C 15 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:358
- 6 - C 23 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:361
- 6 - B 22 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:362
- 8 - C 20 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:363
- 1 - C 20 AND2 0 3 0 1 |sd_top:sd_top1|sd_sig:u4|:364
- 8 - B 22 OR2 ! 0 4 0 1 |sd_top:sd_top1|sd_sig:u4|:366
- 3 - C 14 OR2 s 0 4 0 1 |sd_top:sd_top1|sd_sig:u4|~395~1
- 2 - C 13 OR2 s 0 4 0 1 |sd_top:sd_top1|sd_sig:u4|~396~1
- 3 - B 22 DFFE + ! 0 3 1 0 |sd_top:sd_top1|sd_sig:u4|:403
- 1 - C 21 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:404
- 6 - C 17 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:405
- 3 - C 17 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:406
- 8 - C 15 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:407
- 3 - C 15 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:408
- 7 - C 23 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:409
- 5 - C 23 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:410
- 2 - B 22 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:411
- 6 - C 20 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:412
- 4 - C 16 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:413
- 7 - C 14 OR2 s 0 4 0 2 |sd_top:sd_top1|sd_sig:u4|~451~1
- 1 - C 14 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:455
- 2 - C 14 DFFE + 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:456
- 8 - B 17 DFFE + ! 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:478
- 6 - B 23 DFFE + ! 0 4 1 0 |sd_top:sd_top1|sd_sig:u4|:500
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