📄 sd_if.rpt
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Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
A4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 1/2 3/22( 13%)
A14 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A22 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
A24 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B1 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
B2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
B3 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 4/22( 18%)
B4 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 4/22( 18%)
B5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
B6 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
B7 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 1/22( 4%)
B10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 9/22( 40%)
B11 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
B12 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
B13 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 1/2 5/22( 22%)
B17 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
B20 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 11/22( 50%)
B21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
B22 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 12/22( 54%)
B23 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
C5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
C13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
C14 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 10/22( 45%)
C15 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 10/22( 45%)
C16 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 5/22( 22%)
C17 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 10/22( 45%)
C18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
C20 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 8/22( 36%)
C21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
C22 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C23 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 9/22( 40%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 91/114 ( 79%)
Total logic cells used: 208/576 ( 36%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.22/4 ( 80%)
Total fan-in: 671/2304 ( 29%)
Total input pins required: 50
Total input I/O cell registers required: 0
Total output pins required: 47
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 208
Total flipflops required: 112
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 20/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 8 0 1 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 3 0 8 28/0
B: 8 8 8 8 8 5 3 0 0 8 2 8 0 8 0 0 0 8 0 0 8 8 8 8 0 114/0
C: 0 0 0 0 1 0 0 0 0 0 0 0 0 8 7 8 2 8 8 0 8 8 1 7 0 66/0
Total: 8 16 8 9 9 5 3 0 0 8 2 8 0 16 15 8 2 16 8 0 16 16 12 15 8 208/0
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
57 - - - 22 INPUT ^ 0 0 0 1 ch_addr0
56 - - - 22 INPUT ^ 0 0 0 1 ch_addr1
70 - - - 15 INPUT ^ 0 0 0 1 ch_addr2
62 - - - 19 INPUT ^ 0 0 0 1 ch_addr3
112 - - C -- INPUT ^ 0 0 0 1 ch_addr4
202 - - - 21 INPUT ^ 0 0 0 1 ch_addr5
54 - - - 24 INPUT ^ 0 0 0 1 ch_addr6
190 - - - 15 INPUT ^ 0 0 0 1 ch_addr7
47 - - C -- INPUT ^ 0 0 0 1 ch_addr8
119 - - C -- INPUT ^ 0 0 0 1 ch_addr9
53 - - - 24 INPUT ^ 0 0 0 1 ch_addr10
120 - - C -- INPUT ^ 0 0 0 1 ch_addr11
184 - - - -- INPUT ^ 0 0 0 1 ch_addr12
183 - - - -- INPUT ^ 0 0 0 1 ch_addr13
122 - - C -- INPUT ^ 0 0 0 1 ch_addr14
39 - - C -- INPUT ^ 0 0 0 1 ch_addr15
197 - - - 19 INPUT ^ 0 0 0 1 ch_addr16
191 - - - 15 INPUT ^ 0 0 0 1 ch_addr17
67 - - - 17 INPUT ^ 0 0 0 1 ch_addr18
192 - - - 16 INPUT ^ 0 0 0 1 ch_addr19
189 - - - 14 INPUT ^ 0 0 0 1 ch_addr20
95 - - - 06 INPUT ^ 0 0 0 1 ch_dqm0
135 - - B -- INPUT ^ 0 0 0 1 ch_dqm1
92 - - - 08 INPUT ^ 0 0 0 1 ch_dqm2
64 - - - 18 INPUT ^ 0 0 0 1 ch_dqm3
133 - - B -- INPUT ^ 0 0 0 1 ch_dqm4
179 - - - 12 INPUT ^ 0 0 0 1 ch_dqm5
168 - - - 06 INPUT ^ 0 0 0 1 ch_dqm6
150 - - A -- INPUT ^ 0 0 0 1 ch_dqm7
83 - - - 12 INPUT ^ 0 0 0 1 ch_dqm8
161 - - - 03 INPUT ^ 0 0 0 1 ch_dqm9
96 - - - 05 INPUT ^ 0 0 0 1 ch_dqm10
131 - - B -- INPUT ^ 0 0 0 1 ch_dqm11
208 - - - 24 INPUT ^ 0 0 0 1 ch_dqm12
203 - - - 21 INPUT ^ 0 0 0 1 ch_dqm13
160 - - - 02 INPUT ^ 0 0 0 1 ch_dqm14
127 - - B -- INPUT ^ 0 0 0 1 ch_dqm15
128 - - B -- INPUT ^ 0 0 0 1 ch_num0
86 - - - 11 INPUT ^ 0 0 0 1 ch_num1
170 - - - 08 INPUT ^ 0 0 0 1 ch_num2
177 - - - 11 INPUT ^ 0 0 0 1 ch_num3
85 - - - 11 INPUT ^ 0 0 0 1 ch_num4
87 - - - 10 INPUT ^ 0 0 0 1 ch_num5
163 - - - 04 INPUT ^ 0 0 0 1 ch_num6
99 - - - 04 INPUT ^ 0 0 0 1 ch_num7
196 - - - 18 INPUT ^ 0 0 0 2 ch_req
80 - - - -- INPUT ^ 0 0 0 20 ch_rw
79 - - - -- INPUT G ^ 0 0 0 0 clk
78 - - - -- INPUT G ^ 0 0 0 1 rst_l
182 - - - -- INPUT ^ 0 0 0 1 sdram_en
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\newsdram\sd_if.rpt
sd_if
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
74 - - - 13 OUTPUT 0 1 0 0 ch_ack
19 - - A -- OUTPUT 0 1 0 0 dp_addr0
18 - - A -- OUTPUT 0 1 0 0 dp_addr1
73 - - - 14 OUTPUT 0 1 0 0 dp_addr2
75 - - - 13 OUTPUT 0 1 0 0 dp_addr3
12 - - A -- OUTPUT 0 1 0 0 dp_addr4
16 - - A -- OUTPUT 0 1 0 0 dp_addr5
186 - - - 13 OUTPUT 0 1 0 0 dp_addr6
187 - - - 13 OUTPUT 0 1 0 0 dp_addr7
207 - - - 24 OUTPUT 0 1 0 0 dp_rden
142 - - A -- OUTPUT 0 1 0 0 dp_wren
71 - - - 14 OUTPUT 0 1 0 0 rs_ready
41 - - C -- OUTPUT 0 1 0 0 sd_add0
63 - - - 19 OUTPUT 0 1 0 0 sd_add1
26 - - B -- OUTPUT 0 1 0 0 sd_add2
44 - - C -- OUTPUT 0 1 0 0 sd_add3
46 - - C -- OUTPUT 0 1 0 0 sd_add4
68 - - - 16 OUTPUT 0 1 0 0 sd_add5
69 - - - 16 OUTPUT 0 1 0 0 sd_add6
195 - - - 17 OUTPUT 0 1 0 0 sd_add7
65 - - - 18 OUTPUT 0 1 0 0 sd_add8
38 - - C -- OUTPUT 0 1 0 0 sd_add9
204 - - - 22 OUTPUT 0 1 0 0 sd_add10
11 - - A -- OUTPUT 0 1 0 0 sd_ba0
10 - - A -- OUTPUT 0 1 0 0 sd_ba1
60 - - - 21 OUTPUT 0 1 0 0 sd_cas_l
116 - - C -- OUTPUT 0 1 0 0 sd_cke
193 - - - 17 OUTPUT 0 1 0 0 sd_cs0_l
101 - - - 03 OUTPUT 0 1 0 0 sd_dqm0
25 - - B -- OUTPUT 0 1 0 0 sd_dqm1
158 - - - 01 OUTPUT 0 1 0 0 sd_dqm2
24 - - B -- OUTPUT 0 1 0 0 sd_dqm3
200 - - - 20 OUTPUT 0 1 0 0 sd_dqm4
144 - - A -- OUTPUT 0 1 0 0 sd_dqm5
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