sd_top.map.qmsg

8读8写SDRAM verilog 程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 24 21:35:13 2008 " "Info: Processing started: Thu Jan 24 21:35:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sd_top -c sd_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sd_top -c sd_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sd_if.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sd_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 sd_if " "Info: Found entity 1: sd_if" {  } { { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sd_if " "Info: Elaborating entity \"sd_if\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rw_sd_mach.v 1 1 " "Warning: Using design file rw_sd_mach.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 rw_sd_mach " "Info: Found entity 1: rw_sd_mach" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_sd_mach rw_sd_mach:u1 " "Info: Elaborating entity \"rw_sd_mach\" for hierarchy \"rw_sd_mach:u1\"" {  } { { "sd_if.v" "u1" { Text "D:/newsdram/sd_if.v" 60 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_top.v 1 1 " "Warning: Using design file sd_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_top " "Info: Found entity 1: sd_top" {  } { { "sd_top.v" "" { Text "D:/newsdram/sd_top.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_top sd_top:sd_top1 " "Info: Elaborating entity \"sd_top\" for hierarchy \"sd_top:sd_top1\"" {  } { { "sd_if.v" "sd_top1" { Text "D:/newsdram/sd_if.v" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_cnfg.v 1 1 " "Warning: Using design file sd_cnfg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_cnfg " "Info: Found entity 1: sd_cnfg" {  } { { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_cnfg sd_top:sd_top1\|sd_cnfg:u1 " "Info: Elaborating entity \"sd_cnfg\" for hierarchy \"sd_top:sd_top1\|sd_cnfg:u1\"" {  } { { "sd_top.v" "u1" { Text "D:/newsdram/sd_top.v" 85 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_state.v 1 1 " "Warning: Using design file sd_state.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_state " "Info: Found entity 1: sd_state" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_state sd_top:sd_top1\|sd_state:u2 " "Info: Elaborating entity \"sd_state\" for hierarchy \"sd_top:sd_top1\|sd_state:u2\"" {  } { { "sd_top.v" "u2" { Text "D:/newsdram/sd_top.v" 102 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "sd_state.v(64) " "Info (10264): Verilog HDL Case Statement information at sd_state.v(64): all case item expressions in this case statement are onehot" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_rfrsh.v 1 1 " "Warning: Using design file sd_rfrsh.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_rfrsh " "Info: Found entity 1: sd_rfrsh" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_rfrsh sd_top:sd_top1\|sd_rfrsh:u3 " "Info: Elaborating entity \"sd_rfrsh\" for hierarchy \"sd_top:sd_top1\|sd_rfrsh:u3\"" {  } { { "sd_top.v" "u3" { Text "D:/newsdram/sd_top.v" 109 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_sig.v 1 1 " "Warning: Using design file sd_sig.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_sig " "Info: Found entity 1: sd_sig" {  } { { "sd_sig.v" "" { Text "D:/newsdram/sd_sig.v" 22 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_sig sd_top:sd_top1\|sd_sig:u4 " "Info: Elaborating entity \"sd_sig\" for hierarchy \"sd_top:sd_top1\|sd_sig:u4\"" {  } { { "sd_top.v" "u4" { Text "D:/newsdram/sd_top.v" 137 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "sd_add sd_top1 11 12 " "Warning: Port \"sd_add\" on the entity instantiation of \"sd_top1\" is connected to a signal of width 11. The formal width of the signal in the module is 12.  Extra bits will be left dangling without any fanout logic." {  } { { "sd_if.v" "sd_top1" { Text "D:/newsdram/sd_if.v" 80 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rw_sd_mach:u1\|op_en data_in GND " "Warning: Reduced register \"rw_sd_mach:u1\|op_en\" with stuck data_in port to stuck value GND" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 30 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rw_sd_mach:u1\|op_num\[6\] data_in GND " "Warning: Reduced register \"rw_sd_mach:u1\|op_num\[6\]\" with stuck data_in port to stuck value GND" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 47 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rw_sd_mach:u1\|op_num\[5\] data_in GND " "Warning: Reduced register \"rw_sd_mach:u1\|op_num\[5\]\" with stuck data_in port to stuck value GND" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 47 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rw_sd_mach:u1\|op_num\[4\] data_in GND " "Warning: Reduced register \"rw_sd_mach:u1\|op_num\[4\]\" with stuck data_in port to stuck value GND" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 47 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}