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📄 altsyncram_4d31.tdf

📁 8读8写SDRAM verilog 程序
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			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 40,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a41 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 41,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 41,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a42 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 42,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 42,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a43 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 43,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 43,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a44 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 44,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 44,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a45 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 45,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 45,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a46 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 46,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 46,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a47 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 47,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 47,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a48 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a49 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a50 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a51 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a52 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a53 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 128,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 128,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a54 : stratix_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 2,
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