📄 sd_state.rpt
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| | | | | | | | | | | | +- LC20 state_cntr7
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> * * * * * - - - - - - - - | - * | <-- charge_cycle
LC30 -> * * * * * - - - - - - - - | - * | <-- data_cycle
LC32 -> * * * * * - - - - - - - - | - * | <-- fresh_cycle
LC31 -> * * * * * * * * * * * * * | - * | <-- idle_cycle
LC29 -> * * * * * - - - - - - - - | - * | <-- load_cycle
LC23 -> - - - - - - * - - - - - - | - * | <-- state_cntr0
LC22 -> - - - - - - - * - - - - - | - * | <-- state_cntr1
LC21 -> - - - - - - - - * - - - - | - * | <-- state_cntr2
LC19 -> - - - - - - - - - * - - - | - * | <-- state_cntr3
LC25 -> - - - - - - - - - - * - - | - * | <-- state_cntr4
LC17 -> - - - - - - - - - - - * - | - * | <-- state_cntr5
LC18 -> - - - - - - - - - - - - * | - * | <-- state_cntr6
LC20 -> * - * * * - - - - - - - - | - * | <-- state_cntr7
Pin
8 -> - * - * - - - - - - - - - | - * | <-- charge_req
43 -> - - - - - - - - - - - - - | - - | <-- clk
7 -> * * - * - - - - - - - - - | - * | <-- data_req
5 -> - * * * * - - - - - - - - | - * | <-- fresh_req
6 -> - * - * * - - - - - - - - | - * | <-- load_req
4 -> * * * * * - - - - - - - - | - * | <-- rst_l
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\newsdram\sd_state.rpt
sd_state
** EQUATIONS **
charge_req : INPUT;
clk : INPUT;
data_req : INPUT;
fresh_req : INPUT;
load_req : INPUT;
rst_l : INPUT;
-- Node name is 'charge_cycle' = 'sdram_cycle4'
-- Equation name is 'charge_cycle', location is LC024, type is output.
charge_cycle = DFFE( _EQ001 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ001 = charge_cycle & !data_cycle & !fresh_cycle & !idle_cycle &
!load_cycle & !state_cntr7
# !charge_cycle & data_cycle & !data_req & !fresh_cycle &
!idle_cycle & !load_cycle;
-- Node name is 'data_cycle' = 'sdram_cycle2'
-- Equation name is 'data_cycle', location is LC030, type is output.
data_cycle = DFFE( _EQ002 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ002 = !charge_cycle & !charge_req & !data_cycle & data_req &
!fresh_cycle & !fresh_req & idle_cycle & !load_cycle &
!load_req
# !charge_cycle & data_cycle & data_req & !fresh_cycle &
!idle_cycle & !load_cycle;
-- Node name is 'fresh_cycle' = 'sdram_cycle3'
-- Equation name is 'fresh_cycle', location is LC032, type is output.
fresh_cycle = DFFE( _EQ003 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ003 = !charge_cycle & !data_cycle & !fresh_cycle & fresh_req &
idle_cycle & !load_cycle
# !charge_cycle & !data_cycle & fresh_cycle & !idle_cycle &
!load_cycle & !state_cntr7;
-- Node name is 'idle_cycle' = 'sdram_cycle0'
-- Equation name is 'idle_cycle', location is LC031, type is output.
idle_cycle = DFFE( _EQ004 $ _EQ005, GLOBAL( clk), VCC, rst_l, VCC);
_EQ004 = !charge_cycle & !data_cycle & !fresh_cycle & idle_cycle &
!load_cycle & _X001;
_X001 = EXP(!charge_req & !data_req & !fresh_req & !load_req);
_EQ005 = _X002 & _X003 & _X004 & _X005;
_X002 = EXP(!charge_cycle & !data_cycle & fresh_cycle & !idle_cycle &
!load_cycle & !state_cntr7);
_X003 = EXP(!charge_cycle & !data_cycle & !fresh_cycle & !idle_cycle &
load_cycle & !state_cntr7);
_X004 = EXP( charge_cycle & !data_cycle & !fresh_cycle & !idle_cycle &
!load_cycle & !state_cntr7);
_X005 = EXP(!charge_cycle & data_cycle & !fresh_cycle & !idle_cycle &
!load_cycle);
-- Node name is 'load_cycle' = 'sdram_cycle1'
-- Equation name is 'load_cycle', location is LC029, type is output.
load_cycle = DFFE( _EQ006 $ GND, GLOBAL( clk), rst_l, VCC, VCC);
_EQ006 = !charge_cycle & !data_cycle & !fresh_cycle & !fresh_req &
idle_cycle & !load_cycle & load_req
# !charge_cycle & !data_cycle & !fresh_cycle & !idle_cycle &
load_cycle & !state_cntr7;
-- Node name is 'state_cntr0' = ':130'
-- Equation name is 'state_cntr0', type is output
state_cntr0 = DFFE( idle_cycle $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'state_cntr1' = ':129'
-- Equation name is 'state_cntr1', type is output
state_cntr1 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !idle_cycle & state_cntr0;
-- Node name is 'state_cntr2' = ':128'
-- Equation name is 'state_cntr2', type is output
state_cntr2 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !idle_cycle & state_cntr1;
-- Node name is 'state_cntr3' = ':127'
-- Equation name is 'state_cntr3', type is output
state_cntr3 = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !idle_cycle & state_cntr2;
-- Node name is 'state_cntr4' = ':126'
-- Equation name is 'state_cntr4', type is output
state_cntr4 = DFFE( _EQ010 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !idle_cycle & state_cntr3;
-- Node name is 'state_cntr5' = ':125'
-- Equation name is 'state_cntr5', type is output
state_cntr5 = DFFE( _EQ011 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !idle_cycle & state_cntr4;
-- Node name is 'state_cntr6' = ':124'
-- Equation name is 'state_cntr6', type is output
state_cntr6 = DFFE( _EQ012 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !idle_cycle & state_cntr5;
-- Node name is 'state_cntr7' = ':123'
-- Equation name is 'state_cntr7', type is output
state_cntr7 = DFFE( _EQ013 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !idle_cycle & state_cntr6;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\newsdram\sd_state.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,209K
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