📄 rw_sd_mach.rpt
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-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = DFFE( _EQ064, GLOBAL( clk), VCC, VCC, VCC);
_EQ064 = _LC2_A12 & !_LC5_A12 & _LC6_A1
# !_LC2_A12 & _LC5_A12 & _LC6_A1;
-- Node name is ':305'
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = DFFE( _EQ065, GLOBAL( clk), VCC, VCC, VCC);
_EQ065 = !_LC5_A12 & _LC6_A1;
-- Node name is ':306'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ066);
_EQ066 = ch_req & sdram_setup;
-- Node name is ':384'
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = DFFE( _EQ067, GLOBAL( clk), VCC, VCC, VCC);
_EQ067 = _LC2_C8 & _LC4_B17 & !_LC8_B17
# _LC2_C8 & !_LC4_B17 & _LC8_B17
# ch_addr20 & !_LC2_C8;
-- Node name is ':385'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = DFFE( _EQ068, GLOBAL( clk), VCC, VCC, VCC);
_EQ068 = _LC2_C8 & _LC3_B17 & !_LC6_B17
# _LC2_C8 & !_LC3_B17 & _LC6_B17
# ch_addr19 & !_LC2_C8;
-- Node name is ':386'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = DFFE( _EQ069, GLOBAL( clk), VCC, VCC, VCC);
_EQ069 = _LC2_C8 & !_LC5_B17 & _LC7_B17
# _LC2_C8 & _LC5_B17 & !_LC7_B17
# ch_addr18 & !_LC2_C8;
-- Node name is ':387'
-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = DFFE( _EQ070, GLOBAL( clk), VCC, VCC, VCC);
_EQ070 = _LC2_B17 & _LC2_C8 & !_LC5_B10
# !_LC2_B17 & _LC2_C8 & _LC5_B10
# ch_addr17 & !_LC2_C8;
-- Node name is ':388'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = DFFE( _EQ071, GLOBAL( clk), VCC, VCC, VCC);
_EQ071 = _LC1_B10 & _LC2_C8 & !_LC4_B10
# !_LC1_B10 & _LC2_C8 & _LC4_B10
# ch_addr16 & !_LC2_C8;
-- Node name is ':389'
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = DFFE( _EQ072, GLOBAL( clk), VCC, VCC, VCC);
_EQ072 = !_LC2_B10 & _LC2_C8 & _LC3_B10
# _LC2_B10 & _LC2_C8 & !_LC3_B10
# ch_addr15 & !_LC2_C8;
-- Node name is ':390'
-- Equation name is '_LC8_B10', type is buried
_LC8_B10 = DFFE( _EQ073, GLOBAL( clk), VCC, VCC, VCC);
_EQ073 = _LC2_C8 & !_LC3_A19 & _LC8_B10
# _LC2_C8 & _LC3_A19 & !_LC8_B10
# ch_addr14 & !_LC2_C8;
-- Node name is ':391'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = DFFE( _EQ074, GLOBAL( clk), VCC, VCC, VCC);
_EQ074 = _LC2_C8 & _LC5_A19 & !_LC7_A19
# _LC2_C8 & !_LC5_A19 & _LC7_A19
# ch_addr13 & !_LC2_C8;
-- Node name is ':392'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = DFFE( _EQ075, GLOBAL( clk), VCC, VCC, VCC);
_EQ075 = _LC2_C8 & !_LC6_A19 & _LC8_A19
# _LC2_C8 & _LC6_A19 & !_LC8_A19
# ch_addr12 & !_LC2_C8;
-- Node name is ':393'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = DFFE( _EQ076, GLOBAL( clk), VCC, VCC, VCC);
_EQ076 = _LC2_C8 & !_LC4_A17 & _LC4_A19
# _LC2_C8 & _LC4_A17 & !_LC4_A19
# ch_addr11 & !_LC2_C8;
-- Node name is ':394'
-- Equation name is '_LC1_A17', type is buried
_LC1_A17 = DFFE( _EQ077, GLOBAL( clk), VCC, VCC, VCC);
_EQ077 = _LC1_A17 & _LC2_C8 & !_LC5_A17
# !_LC1_A17 & _LC2_C8 & _LC5_A17
# ch_addr10 & !_LC2_C8;
-- Node name is ':395'
-- Equation name is '_LC8_A17', type is buried
_LC8_A17 = DFFE( _EQ078, GLOBAL( clk), VCC, VCC, VCC);
_EQ078 = _LC2_C8 & !_LC3_A17 & _LC8_A17
# _LC2_C8 & _LC3_A17 & !_LC8_A17
# ch_addr9 & !_LC2_C8;
-- Node name is ':396'
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = DFFE( _EQ079, GLOBAL( clk), VCC, VCC, VCC);
_EQ079 = _LC2_C8 & !_LC3_C6 & _LC6_A17
# _LC2_C8 & _LC3_C6 & !_LC6_A17
# ch_addr8 & !_LC2_C8;
-- Node name is ':397'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = DFFE( _EQ080, GLOBAL( clk), VCC, VCC, VCC);
_EQ080 = _LC2_C8 & _LC5_C6 & !_LC6_C6
# _LC2_C8 & !_LC5_C6 & _LC6_C6
# ch_addr7 & !_LC2_C8;
-- Node name is ':398'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = DFFE( _EQ081, GLOBAL( clk), VCC, VCC, VCC);
_EQ081 = !_LC1_C6 & _LC2_C8 & _LC8_C6
# _LC1_C6 & _LC2_C8 & !_LC8_C6
# ch_addr6 & !_LC2_C8;
-- Node name is ':399'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = DFFE( _EQ082, GLOBAL( clk), VCC, VCC, VCC);
_EQ082 = _LC2_C6 & _LC2_C8 & !_LC4_C9
# !_LC2_C6 & _LC2_C8 & _LC4_C9
# ch_addr5 & !_LC2_C8;
-- Node name is ':400'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = DFFE( _EQ083, GLOBAL( clk), VCC, VCC, VCC);
_EQ083 = _LC2_C8 & _LC3_C9 & !_LC6_C9
# _LC2_C8 & !_LC3_C9 & _LC6_C9
# ch_addr4 & !_LC2_C8;
-- Node name is ':401'
-- Equation name is '_LC8_C9', type is buried
_LC8_C9 = DFFE( _EQ084, GLOBAL( clk), VCC, VCC, VCC);
_EQ084 = _LC2_C8 & !_LC5_C9 & _LC8_C9
# _LC2_C8 & _LC5_C9 & !_LC8_C9
# ch_addr3 & !_LC2_C8;
-- Node name is ':402'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = DFFE( _EQ085, GLOBAL( clk), VCC, VCC, VCC);
_EQ085 = _LC2_C8 & !_LC2_C9 & _LC7_C9
# _LC2_C8 & _LC2_C9 & !_LC7_C9
# ch_addr2 & !_LC2_C8;
-- Node name is ':403'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = DFFE( _EQ086, GLOBAL( clk), VCC, VCC, VCC);
_EQ086 = _LC1_C9 & _LC2_C8 & !_LC4_C6
# !_LC1_C9 & _LC2_C8 & _LC4_C6
# ch_addr1 & !_LC2_C8;
-- Node name is ':404'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = DFFE( _EQ087, GLOBAL( clk), VCC, VCC, VCC);
_EQ087 = _LC2_C8 & !_LC4_C6
# ch_addr0 & !_LC2_C8;
-- Node name is ':405'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = DFFE( _EQ088, GLOBAL( clk), VCC, VCC, VCC);
_EQ088 = _LC2_A19 & _LC2_C8;
-- Node name is ':406'
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = DFFE( _EQ089, GLOBAL( clk), VCC, VCC, VCC);
_EQ089 = _LC2_C8 & _LC7_B10;
-- Node name is ':407'
-- Equation name is '_LC6_B10', type is buried
_LC6_B10 = DFFE( _EQ090, GLOBAL( clk), VCC, VCC, VCC);
_EQ090 = _LC2_C8 & _LC6_B10;
-- Node name is ':408'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = DFFE( _EQ091, GLOBAL( clk), VCC, VCC, VCC);
_EQ091 = _LC1_B17 & _LC2_C8;
Project Information d:\newsdram\rw_sd_mach.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 41,057K
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