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📄 rw_sd_mach.rpt

📁 8读8写SDRAM verilog 程序
💻 RPT
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ch_addr10 : INPUT;
ch_addr11 : INPUT;
ch_addr12 : INPUT;
ch_addr13 : INPUT;
ch_addr14 : INPUT;
ch_addr15 : INPUT;
ch_addr16 : INPUT;
ch_addr17 : INPUT;
ch_addr18 : INPUT;
ch_addr19 : INPUT;
ch_addr20 : INPUT;
ch_num0  : INPUT;
ch_num1  : INPUT;
ch_num2  : INPUT;
ch_num3  : INPUT;
ch_num4  : INPUT;
ch_num5  : INPUT;
ch_num6  : INPUT;
ch_num7  : INPUT;
ch_req   : INPUT;
ch_rw    : INPUT;
clk      : INPUT;
data_cycle : INPUT;
sdram_setup : INPUT;
state_cntr0 : INPUT;

-- Node name is 'add0' 
-- Equation name is 'add0', type is output 
add0     =  _LC1_B17;

-- Node name is 'add1' 
-- Equation name is 'add1', type is output 
add1     =  _LC6_B10;

-- Node name is 'add2' 
-- Equation name is 'add2', type is output 
add2     =  _LC7_B10;

-- Node name is 'add3' 
-- Equation name is 'add3', type is output 
add3     =  _LC2_A19;

-- Node name is 'add4' 
-- Equation name is 'add4', type is output 
add4     =  _LC4_C6;

-- Node name is 'add5' 
-- Equation name is 'add5', type is output 
add5     =  _LC1_C9;

-- Node name is 'add6' 
-- Equation name is 'add6', type is output 
add6     =  _LC7_C9;

-- Node name is 'add7' 
-- Equation name is 'add7', type is output 
add7     =  _LC8_C9;

-- Node name is 'add8' 
-- Equation name is 'add8', type is output 
add8     =  _LC3_C9;

-- Node name is 'add9' 
-- Equation name is 'add9', type is output 
add9     =  _LC2_C6;

-- Node name is 'add10' 
-- Equation name is 'add10', type is output 
add10    =  _LC8_C6;

-- Node name is 'add11' 
-- Equation name is 'add11', type is output 
add11    =  _LC5_C6;

-- Node name is 'add12' 
-- Equation name is 'add12', type is output 
add12    =  _LC6_A17;

-- Node name is 'add13' 
-- Equation name is 'add13', type is output 
add13    =  _LC8_A17;

-- Node name is 'add14' 
-- Equation name is 'add14', type is output 
add14    =  _LC1_A17;

-- Node name is 'add15' 
-- Equation name is 'add15', type is output 
add15    =  _LC4_A19;

-- Node name is 'add16' 
-- Equation name is 'add16', type is output 
add16    =  _LC8_A19;

-- Node name is 'add17' 
-- Equation name is 'add17', type is output 
add17    =  _LC5_A19;

-- Node name is 'add18' 
-- Equation name is 'add18', type is output 
add18    =  _LC8_B10;

-- Node name is 'add19' 
-- Equation name is 'add19', type is output 
add19    =  _LC3_B10;

-- Node name is 'add20' 
-- Equation name is 'add20', type is output 
add20    =  _LC1_B10;

-- Node name is 'add21' 
-- Equation name is 'add21', type is output 
add21    =  _LC2_B17;

-- Node name is 'add22' 
-- Equation name is 'add22', type is output 
add22    =  _LC7_B17;

-- Node name is 'add23' 
-- Equation name is 'add23', type is output 
add23    =  _LC3_B17;

-- Node name is 'add24' 
-- Equation name is 'add24', type is output 
add24    =  _LC4_B17;

-- Node name is 'ch_ack' 
-- Equation name is 'ch_ack', type is output 
ch_ack   =  op_over;

-- Node name is 'data_req' 
-- Equation name is 'data_req', type is output 
data_req =  _LC3_A21;

-- Node name is 'dp_addr0' 
-- Equation name is 'dp_addr0', type is output 
dp_addr0 =  _LC5_A12;

-- Node name is 'dp_addr1' 
-- Equation name is 'dp_addr1', type is output 
dp_addr1 =  _LC2_A12;

-- Node name is 'dp_addr2' 
-- Equation name is 'dp_addr2', type is output 
dp_addr2 =  _LC4_A12;

-- Node name is 'dp_addr3' 
-- Equation name is 'dp_addr3', type is output 
dp_addr3 =  _LC3_A12;

-- Node name is 'dp_addr4' 
-- Equation name is 'dp_addr4', type is output 
dp_addr4 =  _LC8_A12;

-- Node name is 'dp_addr5' 
-- Equation name is 'dp_addr5', type is output 
dp_addr5 =  _LC6_A12;

-- Node name is 'dp_addr6' 
-- Equation name is 'dp_addr6', type is output 
dp_addr6 =  _LC2_A1;

-- Node name is 'dp_addr7' 
-- Equation name is 'dp_addr7', type is output 
dp_addr7 =  _LC8_A1;

-- Node name is 'dp_rden' 
-- Equation name is 'dp_rden', type is output 
dp_rden  =  _LC5_A1;

-- Node name is 'dp_wren' 
-- Equation name is 'dp_wren', type is output 
dp_wren  =  _LC3_A1;

-- Node name is ':100' = 'op_active' 
-- Equation name is 'op_active', location is LC6_C3, type is buried.
op_active = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  data_cycle &  op_en;

-- Node name is ':91' = 'op_en' 
-- Equation name is 'op_en', location is LC4_C3, type is buried.
op_en    = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  data_cycle &  op_en
         #  data_cycle &  state_cntr0;

-- Node name is ':183' = 'op_num0' 
-- Equation name is 'op_num0', location is LC8_C3, type is buried.
op_num0  = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC1_C8 &  _LC7_C3 &  op_num0
         #  _LC1_C8 &  _LC7_C3 & !op_num0;

-- Node name is ':182' = 'op_num1' 
-- Equation name is 'op_num1', location is LC2_C3, type is buried.
op_num1  = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  _LC7_C3 & !op_num0 &  op_num1
         #  _LC1_C8 &  _LC7_C3 &  op_num0 & !op_num1
         # !_LC1_C8 &  _LC7_C3 &  op_num1;

-- Node name is ':181' = 'op_num2' 
-- Equation name is 'op_num2', location is LC4_C11, type is buried.
op_num2  = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC3_C11 &  _LC7_C3 &  op_num2
         #  _LC1_C8 &  _LC3_C11 &  _LC7_C3 & !op_num2
         # !_LC1_C8 &  _LC7_C3 &  op_num2;

-- Node name is ':180' = 'op_num3' 
-- Equation name is 'op_num3', location is LC6_C11, type is buried.
op_num3  = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !_LC5_C11 &  _LC7_C3 &  op_num3
         #  _LC1_C8 &  _LC5_C11 &  _LC7_C3 & !op_num3
         # !_LC1_C8 &  _LC7_C3 &  op_num3;

-- Node name is ':179' = 'op_num4' 
-- Equation name is 'op_num4', location is LC3_C1, type is buried.
op_num4  = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 = !_LC1_C11 &  _LC7_C3 &  op_num4
         #  _LC1_C8 &  _LC1_C11 &  _LC7_C3 & !op_num4
         # !_LC1_C8 &  _LC7_C3 &  op_num4;

-- Node name is ':178' = 'op_num5' 
-- Equation name is 'op_num5', location is LC6_C1, type is buried.
op_num5  = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 = !_LC4_C1 &  _LC7_C3 &  op_num5
         #  _LC1_C8 &  _LC4_C1 &  _LC7_C3 & !op_num5
         # !_LC1_C8 &  _LC7_C3 &  op_num5;

-- Node name is ':177' = 'op_num6' 
-- Equation name is 'op_num6', location is LC5_C1, type is buried.
op_num6  = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !_LC7_C1 &  _LC7_C3 &  op_num6
         #  _LC1_C8 &  _LC7_C1 &  _LC7_C3 & !op_num6
         # !_LC1_C8 &  _LC7_C3 &  op_num6;

-- Node name is ':176' = 'op_num7' 
-- Equation name is 'op_num7', location is LC1_C3, type is buried.
op_num7  = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 = !_LC1_C1 &  _LC7_C3 &  op_num7
         #  _LC1_C1 &  _LC1_C8 &  _LC7_C3 & !op_num7
         # !_LC1_C8 &  _LC7_C3 &  op_num7;

-- Node name is ':228' = 'op_over' 
-- Equation name is 'op_over', location is LC3_C3, type is buried.
op_over  = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  data_cycle &  op_over
         #  data_cycle &  _LC5_C3 &  op_active;

-- Node name is 'rs_ready' 
-- Equation name is 'rs_ready', type is output 
rs_ready =  _LC2_C8;

-- Node name is ':269' = 'rs_ready_delay0' 
-- Equation name is 'rs_ready_delay0', location is LC1_A19, type is buried.
rs_ready_delay0 = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  data_cycle &  _LC2_C8;

-- Node name is ':268' = 'rs_ready_delay1' 
-- Equation name is 'rs_ready_delay1', location is LC7_A17, type is buried.
rs_ready_delay1 = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  data_cycle &  rs_ready_delay0;

-- Node name is ':267' = 'rs_ready_delay2' 
-- Equation name is 'rs_ready_delay2', location is LC2_A17, type is buried.
rs_ready_delay2 = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  data_cycle &  rs_ready_delay1;

-- Node name is ':266' = 'rs_ready_delay3' 
-- Equation name is 'rs_ready_delay3', location is LC1_A1, type is buried.
rs_ready_delay3 = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  data_cycle &  rs_ready_delay2;

-- Node name is ':265' = 'rs_ready_delay4' 
-- Equation name is 'rs_ready_delay4', location is LC4_A1, type is buried.
rs_ready_delay4 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 =  data_cycle &  rs_ready_delay3;

-- Node name is 'wr_l' 
-- Equation name is 'wr_l', type is output 

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