📄 rw_sd_mach.rpt
字号:
91 - - B -- INPUT 0 0 0 1 ch_addr16
22 - - B -- INPUT 0 0 0 1 ch_addr17
21 - - B -- INPUT 0 0 0 1 ch_addr18
137 - - - 19 INPUT 0 0 0 1 ch_addr19
89 - - B -- INPUT 0 0 0 1 ch_addr20
109 - - - 01 INPUT 0 0 0 1 ch_num0
82 - - C -- INPUT 0 0 0 1 ch_num1
26 - - C -- INPUT 0 0 0 1 ch_num2
30 - - C -- INPUT 0 0 0 1 ch_num3
27 - - C -- INPUT 0 0 0 1 ch_num4
112 - - - 03 INPUT 0 0 0 1 ch_num5
32 - - C -- INPUT 0 0 0 1 ch_num6
31 - - C -- INPUT 0 0 0 1 ch_num7
140 - - - 21 INPUT 0 0 0 1 ch_req
56 - - - -- INPUT 0 0 0 4 ch_rw
55 - - - -- INPUT G 0 0 0 0 clk
54 - - - -- INPUT 0 0 0 11 data_cycle
143 - - - 24 INPUT 0 0 0 1 sdram_setup
124 - - - -- INPUT 0 0 0 1 state_cntr0
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - B -- OUTPUT 0 1 0 0 add0
88 - - B -- OUTPUT 0 1 0 0 add1
87 - - B -- OUTPUT 0 1 0 0 add2
8 - - A -- OUTPUT 0 1 0 0 add3
80 - - C -- OUTPUT 0 1 0 0 add4
83 - - C -- OUTPUT 0 1 0 0 add5
78 - - C -- OUTPUT 0 1 0 0 add6
121 - - - 10 OUTPUT 0 1 0 0 add7
64 - - - 10 OUTPUT 0 1 0 0 add8
70 - - - 05 OUTPUT 0 1 0 0 add9
117 - - - 06 OUTPUT 0 1 0 0 add10
79 - - C -- OUTPUT 0 1 0 0 add11
12 - - A -- OUTPUT 0 1 0 0 add12
135 - - - 18 OUTPUT 0 1 0 0 add13
7 - - A -- OUTPUT 0 1 0 0 add14
10 - - A -- OUTPUT 0 1 0 0 add15
14 - - A -- OUTPUT 0 1 0 0 add16
136 - - - 19 OUTPUT 0 1 0 0 add17
86 - - B -- OUTPUT 0 1 0 0 add18
90 - - B -- OUTPUT 0 1 0 0 add19
92 - - B -- OUTPUT 0 1 0 0 add20
18 - - B -- OUTPUT 0 1 0 0 add21
23 - - B -- OUTPUT 0 1 0 0 add22
46 - - - 17 OUTPUT 0 1 0 0 add23
20 - - B -- OUTPUT 0 1 0 0 add24
81 - - C -- OUTPUT 0 1 0 0 ch_ack
9 - - A -- OUTPUT 0 1 0 0 data_req
59 - - - 12 OUTPUT 0 1 0 0 dp_addr0
122 - - - 12 OUTPUT 0 1 0 0 dp_addr1
99 - - A -- OUTPUT 0 1 0 0 dp_addr2
63 - - - 11 OUTPUT 0 1 0 0 dp_addr3
98 - - A -- OUTPUT 0 1 0 0 dp_addr4
97 - - A -- OUTPUT 0 1 0 0 dp_addr5
101 - - A -- OUTPUT 0 1 0 0 dp_addr6
95 - - A -- OUTPUT 0 1 0 0 dp_addr7
73 - - - 02 OUTPUT 0 1 0 0 dp_rden
100 - - A -- OUTPUT 0 1 0 0 dp_wren
68 - - - 07 OUTPUT 0 1 0 0 rs_ready
102 - - A -- OUTPUT 0 1 0 0 wr_l
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 11 AND2 0 2 0 1 |lpm_add_sub:410|addcore:adder|:121
- 5 - C 11 AND2 0 3 0 1 |lpm_add_sub:410|addcore:adder|:125
- 1 - C 11 AND2 0 4 0 4 |lpm_add_sub:410|addcore:adder|:129
- 4 - C 01 AND2 0 2 0 1 |lpm_add_sub:410|addcore:adder|:133
- 7 - C 01 AND2 0 3 0 1 |lpm_add_sub:410|addcore:adder|:137
- 1 - C 01 AND2 0 4 0 1 |lpm_add_sub:410|addcore:adder|:141
- 7 - A 12 AND2 0 2 0 1 |lpm_add_sub:411|addcore:adder|:121
- 1 - A 12 AND2 0 4 0 3 |lpm_add_sub:411|addcore:adder|:129
- 7 - A 01 AND2 0 3 0 2 |lpm_add_sub:411|addcore:adder|:137
- 2 - C 09 AND2 0 2 0 4 |lpm_add_sub:412|addcore:adder|:155
- 5 - C 09 AND2 0 2 0 1 |lpm_add_sub:412|addcore:adder|:159
- 6 - C 09 AND2 0 3 0 1 |lpm_add_sub:412|addcore:adder|:163
- 4 - C 09 AND2 0 4 0 4 |lpm_add_sub:412|addcore:adder|:167
- 1 - C 06 AND2 0 2 0 1 |lpm_add_sub:412|addcore:adder|:171
- 6 - C 06 AND2 0 3 0 1 |lpm_add_sub:412|addcore:adder|:175
- 3 - C 06 AND2 0 4 0 4 |lpm_add_sub:412|addcore:adder|:179
- 3 - A 17 AND2 0 2 0 1 |lpm_add_sub:412|addcore:adder|:183
- 5 - A 17 AND2 0 3 0 1 |lpm_add_sub:412|addcore:adder|:187
- 4 - A 17 AND2 0 4 0 4 |lpm_add_sub:412|addcore:adder|:191
- 6 - A 19 AND2 0 2 0 1 |lpm_add_sub:412|addcore:adder|:195
- 7 - A 19 AND2 0 3 0 1 |lpm_add_sub:412|addcore:adder|:199
- 3 - A 19 AND2 0 4 0 4 |lpm_add_sub:412|addcore:adder|:203
- 2 - B 10 AND2 0 2 0 1 |lpm_add_sub:412|addcore:adder|:207
- 4 - B 10 AND2 0 3 0 1 |lpm_add_sub:412|addcore:adder|:211
- 5 - B 10 AND2 0 4 0 4 |lpm_add_sub:412|addcore:adder|:215
- 5 - B 17 AND2 0 2 0 1 |lpm_add_sub:412|addcore:adder|:219
- 6 - B 17 AND2 0 3 0 1 |lpm_add_sub:412|addcore:adder|:223
- 8 - B 17 AND2 0 4 0 1 |lpm_add_sub:412|addcore:adder|:227
- 1 - A 07 LCELL s 1 0 1 0 wr_l~1
- 4 - C 03 DFFE + 2 0 0 2 op_en (:91)
- 7 - C 03 AND2 1 1 0 8 :96
- 6 - C 03 DFFE + 1 1 0 3 op_active (:100)
- 1 - C 08 AND2 0 2 0 8 :102
- 1 - C 03 DFFE + 0 3 0 1 op_num7 (:176)
- 5 - C 01 DFFE + 0 3 0 2 op_num6 (:177)
- 6 - C 01 DFFE + 0 3 0 3 op_num5 (:178)
- 3 - C 01 DFFE + 0 3 0 4 op_num4 (:179)
- 6 - C 11 DFFE + 0 3 0 2 op_num3 (:180)
- 4 - C 11 DFFE + 0 3 0 3 op_num2 (:181)
- 2 - C 03 DFFE + 0 3 0 4 op_num1 (:182)
- 8 - C 03 DFFE + 0 2 0 5 op_num0 (:183)
- 1 - C 02 OR2 ! 1 2 0 1 :189
- 2 - C 01 OR2 ! 1 2 0 1 :194
- 8 - C 01 OR2 ! 1 2 0 1 :199
- 2 - C 11 OR2 ! 1 2 0 1 :204
- 8 - C 11 OR2 ! 1 2 0 1 :209
- 7 - C 11 OR2 ! 2 2 0 1 :214
- 5 - C 03 OR2 s 1 2 0 1 ~222~1
- 3 - C 03 DFFE + 1 2 1 2 op_over (:228)
- 5 - A 01 AND2 2 0 1 0 :231
- 2 - C 08 DFFE + 0 2 1 26 :236
- 4 - A 01 DFFE + 1 1 0 1 rs_ready_delay4 (:265)
- 1 - A 01 DFFE + 1 1 0 1 rs_ready_delay3 (:266)
- 2 - A 17 DFFE + 1 1 0 1 rs_ready_delay2 (:267)
- 7 - A 17 DFFE + 1 1 0 1 rs_ready_delay1 (:268)
- 1 - A 19 DFFE + 1 1 0 1 rs_ready_delay0 (:269)
- 3 - A 01 AND2 1 1 1 1 :270
- 6 - A 01 OR2 2 1 0 8 :272
- 8 - A 01 DFFE + 0 3 1 0 :298
- 2 - A 01 DFFE + 0 2 1 1 :299
- 6 - A 12 DFFE + 0 3 1 1 :300
- 8 - A 12 DFFE + 0 2 1 2 :301
- 3 - A 12 DFFE + 0 3 1 1 :302
- 4 - A 12 DFFE + 0 3 1 2 :303
- 2 - A 12 DFFE + 0 2 1 3 :304
- 5 - A 12 DFFE + 0 1 1 4 :305
- 3 - A 21 AND2 2 0 1 0 :306
- 4 - B 17 DFFE + 1 2 1 0 :384
- 3 - B 17 DFFE + 1 2 1 1 :385
- 7 - B 17 DFFE + 1 2 1 2 :386
- 2 - B 17 DFFE + 1 2 1 3 :387
- 1 - B 10 DFFE + 1 2 1 1 :388
- 3 - B 10 DFFE + 1 2 1 2 :389
- 8 - B 10 DFFE + 1 2 1 3 :390
- 5 - A 19 DFFE + 1 2 1 1 :391
- 8 - A 19 DFFE + 1 2 1 2 :392
- 4 - A 19 DFFE + 1 2 1 3 :393
- 1 - A 17 DFFE + 1 2 1 1 :394
- 8 - A 17 DFFE + 1 2 1 2 :395
- 6 - A 17 DFFE + 1 2 1 3 :396
- 5 - C 06 DFFE + 1 2 1 1 :397
- 8 - C 06 DFFE + 1 2 1 2 :398
- 2 - C 06 DFFE + 1 2 1 3 :399
- 3 - C 09 DFFE + 1 2 1 1 :400
- 8 - C 09 DFFE + 1 2 1 2 :401
- 7 - C 09 DFFE + 1 2 1 3 :402
- 1 - C 09 DFFE + 1 2 1 1 :403
- 4 - C 06 DFFE + 1 1 1 2 :404
- 2 - A 19 DFFE + 0 1 1 0 :405
- 7 - B 10 DFFE + 0 1 1 0 :406
- 6 - B 10 DFFE + 0 1 1 0 :407
- 1 - B 17 DFFE + 0 1 1 0 :408
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 9/ 48( 18%) 12/ 48( 25%) 3/16( 18%) 13/16( 81%) 0/16( 0%)
B: 8/ 96( 8%) 6/ 48( 12%) 5/ 48( 10%) 5/16( 31%) 9/16( 56%) 0/16( 0%)
C: 13/ 96( 13%) 19/ 48( 39%) 0/ 48( 0%) 9/16( 56%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 50 clk
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** EQUATIONS **
ch_addr0 : INPUT;
ch_addr1 : INPUT;
ch_addr2 : INPUT;
ch_addr3 : INPUT;
ch_addr4 : INPUT;
ch_addr5 : INPUT;
ch_addr6 : INPUT;
ch_addr7 : INPUT;
ch_addr8 : INPUT;
ch_addr9 : INPUT;
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