📄 rw_sd_mach.rpt
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Project Information d:\newsdram\rw_sd_mach.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/24/2008 21:35:49
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
rw_sd_mach
EPF10K10TC144-3 35 39 0 0 0 % 92 15 %
User Pins: 35 39 0
Project Information d:\newsdram\rw_sd_mach.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'rst_l'
Warning: Ignored unnecessary INPUT pin 'state_cntr7'
Warning: Ignored unnecessary INPUT pin 'state_cntr6'
Warning: Ignored unnecessary INPUT pin 'state_cntr5'
Warning: Ignored unnecessary INPUT pin 'state_cntr4'
Warning: Ignored unnecessary INPUT pin 'state_cntr3'
Warning: Ignored unnecessary INPUT pin 'state_cntr2'
Warning: Ignored unnecessary INPUT pin 'state_cntr1'
Project Information d:\newsdram\rw_sd_mach.rpt
** FILE HIERARCHY **
|lpm_add_sub:410|
|lpm_add_sub:410|addcore:adder|
|lpm_add_sub:410|altshift:result_ext_latency_ffs|
|lpm_add_sub:410|altshift:carry_ext_latency_ffs|
|lpm_add_sub:410|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:411|
|lpm_add_sub:411|addcore:adder|
|lpm_add_sub:411|altshift:result_ext_latency_ffs|
|lpm_add_sub:411|altshift:carry_ext_latency_ffs|
|lpm_add_sub:411|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:412|
|lpm_add_sub:412|addcore:adder|
|lpm_add_sub:412|altshift:result_ext_latency_ffs|
|lpm_add_sub:412|altshift:carry_ext_latency_ffs|
|lpm_add_sub:412|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
***** Logic for device 'rw_sd_mach' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
s s
d t
r c a c
R a R R R h R R R R R c c t d c R R R c R h R
E m E E E _ E E E E E h h e p h E E E h E c _ E c
S _ S S c S a S S S S S G _ _ _ V _ _ S S S _ S h a S h
E s E E h G E d a a V E E E E G E N a a c C a a E E a E V a E _ d E _
R e R R _ N R d d d C R R R R N R D d d n C d a d R R d R C d R n d R n
V t V V r D V r d d C V V V V D V I d d t I d d d V V d V C d V u r V u
E u E E e I E 1 1 1 I E E E E I E N r r r N r d r E E 1 E I r E m 1 E m
D p D D q O D 9 7 3 O D D D D O D T 0 1 0 T 1 7 5 D D 0 D O 3 D 5 5 D 0
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
add14 | 7 102 | wr_l
add3 | 8 101 | dp_addr6
data_req | 9 100 | dp_wren
add15 | 10 99 | dp_addr2
ch_addr10 | 11 98 | dp_addr4
add12 | 12 97 | dp_addr5
ch_addr9 | 13 96 | ch_addr11
add16 | 14 95 | dp_addr7
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
add0 | 17 92 | add20
add21 | 18 91 | ch_addr16
ch_addr14 | 19 EPF10K10TC144-3 90 | add19
add24 | 20 89 | ch_addr20
ch_addr18 | 21 88 | add1
ch_addr17 | 22 87 | add2
add22 | 23 86 | add18
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
ch_num2 | 26 83 | add5
ch_num4 | 27 82 | ch_num1
ch_addr6 | 28 81 | ch_ack
ch_addr2 | 29 80 | add4
ch_num3 | 30 79 | add11
ch_num7 | 31 78 | add6
ch_num6 | 32 77 | ^MSEL0
ch_addr4 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | dp_rden
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G c R R R V a c R c G R V V d c c G G d R V R d a R G c r R a V R
E E E N h E E E C d h E h N E C C a l h N N p E C E p d E N h s E d C E
S S S D _ S S S C d _ S _ D S C C t k _ D D _ S C S _ d S D _ _ S d C S
E E E I a E E E I 2 a E a I E I I a r I I a E I E a 8 E I a r E 9 I E
R R R O d R R R O 3 d R d O R N N _ w N N d R O R d R O d e R O R
V V V d V V V d V d V T T c T T d V V d V d a V V
E E E r E E E r E r E y r E E r E r d E E
D D D 1 D D D 1 D 8 D c 0 D D 3 D 7 y D D
3 2 l
e
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
A12 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
A17 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A19 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
B17 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
C6 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
C8 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
C9 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C11 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 68/96 ( 70%)
Total logic cells used: 92/576 ( 15%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.14/4 ( 78%)
Total fan-in: 289/2304 ( 12%)
Total input pins required: 35
Total input I/O cell registers required: 0
Total output pins required: 39
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 92
Total flipflops required: 50
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 2/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 0 0 0 0 1 0 0 0 0 8 0 0 0 0 0 8 0 8 0 1 0 0 0 34/0
B: 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 16/0
C: 8 1 8 0 0 7 0 2 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 42/0
Total: 16 1 8 0 0 7 1 2 8 8 8 8 0 0 0 0 0 16 0 8 0 1 0 0 0 92/0
Device-Specific Information: d:\newsdram\rw_sd_mach.rpt
rw_sd_mach
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT 0 0 0 1 ch_addr0
125 - - - -- INPUT 0 0 0 1 ch_addr1
29 - - C -- INPUT 0 0 0 1 ch_addr2
114 - - - 04 INPUT 0 0 0 1 ch_addr3
33 - - C -- INPUT 0 0 0 1 ch_addr4
120 - - - 09 INPUT 0 0 0 1 ch_addr5
28 - - C -- INPUT 0 0 0 1 ch_addr6
67 - - - 08 INPUT 0 0 0 1 ch_addr7
49 - - - 14 INPUT 0 0 0 1 ch_addr8
13 - - A -- INPUT 0 0 0 1 ch_addr9
11 - - A -- INPUT 0 0 0 1 ch_addr10
96 - - A -- INPUT 0 0 0 1 ch_addr11
47 - - - 16 INPUT 0 0 0 1 ch_addr12
41 - - - 20 INPUT 0 0 0 1 ch_addr13
19 - - B -- INPUT 0 0 0 1 ch_addr14
111 - - - 02 INPUT 0 0 0 1 ch_addr15
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