sd_top.tan.summary

8读8写SDRAM verilog 程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.800 ns
From           : ch_req
To             : sd_top:sd_top1|sd_state:u2|sdram_cycle[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.900 ns
From           : sd_top:sd_top1|sd_state:u2|sdram_cycle[2]
To             : dp_rden
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.000 ns
From           : ch_rw
To             : dp_rden
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.900 ns
From           : ch_addr[19]
To             : rw_sd_mach:u1|add[23]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 78.74 MHz ( period = 12.700 ns )
From           : sd_top:sd_top1|sd_cnfg:u1|fresh_req
To             : sd_top:sd_top1|sd_state:u2|sdram_cycle[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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