rw_sd_mach.v

8读8写SDRAM verilog 程序

`timescale 1 ns /  100 ps
module rw_sd_mach(
		clk,rst_l,
		ch_req,ch_addr,ch_rw,ch_num,ch_ack,
		dp_addr,dp_wren,dp_rden,
		data_req,add,wr_l,
		rs_ready,
		sdram_setup,
		data_cycle,
		state_cntr
	);
input			clk,rst_l;
input			ch_req;
input	[20:0]	ch_addr;
input			ch_rw;
input	[7:0]	ch_num;
output			ch_ack;

output	[7:0]	dp_addr;
output			dp_wren,dp_rden;
output			data_req;
output  [24:0]	add;
output			wr_l;
output			rs_ready;
input			data_cycle;
input			sdram_setup;
input[7:0]		state_cntr;


reg		op_en;
reg		op_over;
always @(posedge clk)
	if(data_cycle)
	 	if(state_cntr[0])
			op_en<= #1 1'b1;
		else
			op_en<= #1 op_en;
	else
		op_en<= #1 1'b0;

reg	[7:0]	op_num;

reg	op_active;


always @(posedge clk)
	if(data_cycle)
		if(op_en)begin
			if(op_active && !op_over)
				op_num<= #1 op_num+8'h1;
			else
				op_num<= #1 op_num;	
			op_active<= #1 1'b1;
		end
		else begin
			op_num<=#1 8'h0;
			op_active<=#1 1'b0;
		end
	else begin
		op_num<= #1 8'h0;
		op_active<= #1 1'b0;
	end

always @(posedge clk)
	if(data_cycle)
		op_over<= #1 ((op_num>=ch_num) & op_active) | op_over;
	else
		op_over<= #1 1'b0;
reg	rs_ready;
always @(posedge clk)
	rs_ready<= #1 op_active & ~op_over;

assign	data_req=ch_req & sdram_setup;

assign	ch_ack=op_over;

assign	dp_rden=data_cycle & ~ch_rw;

reg[7:0]		rs_ready_delay;
always @(posedge clk)begin
	if(data_cycle)
		rs_ready_delay<= #1 {rs_ready_delay[6:0],rs_ready};
	else
		rs_ready_delay<=8'd0;
end
assign	dp_wren=rs_ready_delay[4] & ch_rw;

reg[7:0]	dp_addr;
always @(posedge clk)
	if(dp_rden || dp_wren)
		dp_addr<= #1 dp_addr+8'd1;
	else
		dp_addr<= #1 8'd0;

assign	wr_l=ch_rw;
reg [24:0]	add;
always @(posedge clk)begin
	if(rs_ready)
		add<= #1 add+24'h10;
	else
		add<= #1 {ch_addr,4'd0};
end

endmodule