mem_ctrl1.v

8读8写SDRAM verilog 程序

/*======================================================
birth 060630
flag	051024
=======================================================*/
module mem_ctrl1(
				clk,                // sdram clock
				rst_l,              // reset signal

				wda,wdb,wdc,wdd,wde,wdf,wdg,wdh,
				wada,wadb,wadc,wadd,wade,wadf,wadg,wadh,
				wreqa,wreqb,wreqc,wreqd,wreqe,wreqf,wreqg,wreqh,
				wnuma,wnumb,wnumc,wnumd,wnume,wnumf,wnumg,wnumh,
				wacka,wackb,wackc,wackd,wacke,wackf,wackg,wackh,
				wma,wmb,wmc,wmd,wme,wmf,wmg,wmh,
				rada,radb,radc,radd,rade,radf,radg,radh,
				rreqa,rreqb,rreqc,rreqd,rreqe,rreqf,rreqg,rreqh,
				rnuma,rnumb,rnumc,rnumd,rnume,rnumf,rnumg,rnumh,
				racka,rackb,rackc,rackd,racke,rackf,rackg,rackh,
				csa,csb,csc,csd,cse,csf,csg,csh,
				dp_addr,dp_rden,dp_wren,//dp_data,
				//sdram_port
				sd_dq,
				sd_cke,             // sdram clock enable
				sd_ba,              // sdram bank address
				sd_cs0_l,           // sdram chip select 0
				sd_ras_l,           // sdram row address
				sd_cas_l,           // sdram column select
				sd_we_l,            // sdram write enable
				sd_add,             // sdram address
				sd_dqm,             // sdram data qual mask
                sdram_setup,		// sdram setup completed
				sdram_en,
				ch_rw
				);

input          	clk;
input          	rst_l;

input	[127:0]	wda,wdb,wdc,wdd,wde,wdf,wdg,wdh;

input	[20:0]	wada,wadb,wadc,wadd,wade,wadf,wadg,wadh;
input			wreqa,wreqb,wreqc,wreqd,wreqe,wreqf,wreqg,wreqh;
input	[7:0]	wnuma,wnumb,wnumc,wnumd,wnume,wnumf,wnumg,wnumh;
output			wacka,wackb,wackc,wackd,wacke,wackf,wackg,wackh;

input	[15:0]	wma,wmb,wmc,wmd,wme,wmf,wmg,wmh;
input	[20:0]	rada,radb,radc,radd,rade,radf,radg,radh;
input			rreqa,rreqb,rreqc,rreqd,rreqe,rreqf,rreqg,rreqh;
input	[7:0]	rnuma,rnumb,rnumc,rnumd,rnume,rnumf,rnumg,rnumh;
output			racka,rackb,rackc,rackd,racke,rackf,rackg,rackh;
output			csa,csb,csc,csd,cse,csf,csg,csh;

output	[7:0]	dp_addr;

output			dp_rden,dp_wren;
//output	[127:0]	dp_data;
output	[127:0]	sd_dq;
output         	sd_cke;
output [1:0]   	sd_ba;
output         	sd_cs0_l,
               	sd_ras_l,
				sd_cas_l,
				sd_we_l;
output [10:0]  	sd_add;
output [15:0]   sd_dqm;              
output          sdram_setup;
input			sdram_en;
output			ch_rw;
/*=================writing data seledt pipeline=======================*/
wire [3:0]	w0sel;
wire [1:0]	w1sel;
wire 		w2sel;
wire [127:0] w2buf;
wire [15:0]	wdqm;
wr_sel_pipe wr_sel_pile1(
			.clk(clk),.w0sel(w0sel),.w1sel(w1sel),.w2sel(w2sel),
			.wda(wda),.wdb(wdb),.wdc(wdc),.wdd(wdd),.wde(wde),.wdf(wdf),.wdg(wdg),.wdh(wdh),		
			.wma(wma),.wmb(wmb),.wmc(wmc),.wmd(wmd),.wme(wme),.wmf(wmf),.wmg(wmg),.wmh(wmh),
			.w2buf(w2buf),
			.wdqm(wdqm)
			);

//assign sd_dq=(~sd_we_l) ? w2buf :128'hzzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz;
assign 	sd_dq=w2buf;
//=========================req machine================================
wire 		term_l;
wire [7:0]	ch_num;
wire		ch_rw;
wire [20:0]	ch_addr;
wire 		ch_req;
wire [7:0]	wack,rack;

assign wacka=wack[0];
assign wackb=wack[1];
assign wackc=wack[2];
assign wackd=wack[3];
assign wacke=wack[4];
assign wackf=wack[5];
assign wackg=wack[6];
assign wackh=wack[7];

assign racka=rack[0];
assign rackb=rack[1];
assign rackc=rack[2];
assign rackd=rack[3];
assign racke=rack[4];
assign rackf=rack[5];
assign rackg=rack[6];
assign rackh=rack[7];

wire [7:0]	wcs;
wire		rs_ready;
wire		read_lock;
wire 		ch_ack;
wire [2:0]	ch_sur;
para_mach_d  para_mach_inst(
				.clk(clk),
				.wada(wada),.wadb(wadb),.wadc(wadc),.wadd(wadd),.wade(wade),.wadf(wadf),.wadg(wadg),.wadh(wadh),
				.wreqa(wreqa),.wreqb(wreqb),.wreqc(wreqc),.wreqd(wreqd),.wreqe(wreqe),.wreqf(wreqf),.wreqg(wreqg),.wreqh(wreqh),
				.wnuma(wnuma),.wnumb(wnumb),.wnumc(wnumc),.wnumd(wnumd),.wnume(wnume),.wnumf(wnumf),.wnumg(wnumg),.wnumh(wnumh),
				.wack(wack),

				.rada(rada),.radb(radb),.radc(radc),.radd(radd),.rade(rade),.radf(radf),.radg(radg),.radh(radh),
				.rreqa(rreqa),.rreqb(rreqb),.rreqc(rreqc),.rreqd(rreqd),.rreqe(rreqe),.rreqf(rreqf),.rreqg(rreqg),.rreqh(rreqh),
				.rnuma(rnuma),.rnumb(rnumb),.rnumc(rnumc),.rnumd(rnumd),.rnume(rnume),.rnumf(rnumf),.rnumg(rnumg),.rnumh(rnumh),
				.rack(rack),

				.w0sel(w0sel),.w1sel(w1sel),.w2sel(w2sel),
				.ch_num(ch_num),.ch_rw(ch_rw),.ch_addr(ch_addr),.ch_ack(ch_ack),.ch_req(ch_req),.ch_sur(ch_sur)//,
				);
//==========================================write or read sdram machine===================================

reg	csa,csb,csc,csd,cse,csf,csg,csh;

always @(posedge clk)begin
 csa<=ch_sur==3'd0;
 csb<=ch_sur==3'd1;
 csc<=ch_sur==3'd2;
 csd<=ch_sur==3'd3;
 cse<=ch_sur==3'd4;
 csf<=ch_sur==3'd5;
 csg<=ch_sur==3'd6;
 csh<=ch_sur==3'd7;
end

sd_if sd_if1(
				.ch_req(ch_req),.ch_addr(ch_addr),.ch_rw(ch_rw),.ch_num(ch_num),.ch_ack(ch_ack),.ch_dqm(wdqm),
				.dp_addr(dp_addr),.dp_wren(dp_wren),.dp_rden(dp_rden),
				.clk(clk),                	// sdram clock
				.rst_l(rst_l),              // reset signalk,                // sdram clock

				.sdram_en(sdram_en),
				.sd_cke(sd_cke),            // sdram clock enable
				.sd_ba(sd_ba),              // sdram bank address
				.sd_cs0_l(sd_cs0_l),        // sdram chip select 0
				.sd_ras_l(sd_ras_l),        // sdram row address
				.sd_cas_l(sd_cas_l),        // sdram column select
				.sd_we_l(sd_we_l),          // sdram write enable
				.sd_add(sd_add),            // sdram address
				.sd_dqm(sd_dqm),	        // sdram data qual mask
				.sdram_setup(sdram_setup)
	);
endmodule