sd_cnfg.rpt

8读8写SDRAM verilog 程序

Device-Specific Information:                           d:\newsdram\sd_cnfg.rpt
sd_cnfg

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC17 charge_req
        | +----------------- LC19 fresh_req
        | | +--------------- LC20 load_req
        | | | +------------- LC18 sdram_setup
        | | | | +----------- LC25 sdram_en1
        | | | | | +--------- LC24 sdram_en2
        | | | | | | +------- LC21 state3
        | | | | | | | +----- LC22 state2
        | | | | | | | | +--- LC23 state1
        | | | | | | | | | +- LC29 state0
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - | - * | <-- charge_req
LC19 -> - * - - - - - - - - | - * | <-- fresh_req
LC20 -> - - * - - - - - - - | - * | <-- load_req
LC18 -> - - - * - - - - - - | - * | <-- sdram_setup
LC25 -> - - - - - * - - - - | - * | <-- sdram_en1
LC24 -> * * * * - - - - - * | - * | <-- sdram_en2
LC21 -> * * * * - - * * * * | - * | <-- state3
LC22 -> * * * * - - * * * * | - * | <-- state2
LC23 -> * * * * - - * * * * | - * | <-- state1
LC29 -> * * * * - - * * * * | - * | <-- state0

Pin
4    -> * - - - - - - - * - | - * | <-- charge_cycle
43   -> - - - - - - - - - - | - - | <-- clk
5    -> - * - - - - - * * * | - * | <-- fresh_cycle
7    -> - - * - - - * * * * | - * | <-- load_cycle
1    -> - - - * - - - - - - | - * | <-- rst_l
6    -> - - - - * - - - - - | - * | <-- sdram_en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                           d:\newsdram\sd_cnfg.rpt
sd_cnfg

** EQUATIONS **

charge_cycle : INPUT;
clk      : INPUT;
fresh_cycle : INPUT;
load_cycle : INPUT;
rst_l    : INPUT;
sdram_en : INPUT;

-- Node name is 'charge_req' = ':208' 
-- Equation name is 'charge_req', type is output 
 charge_req = TFFE( _EQ001, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ001 =  charge_cycle &  charge_req &  state0 & !state1 & !state2 & 
             !state3
         #  charge_req &  sdram_en2 & !state0 & !state1 & !state2 & !state3
         # !charge_cycle & !charge_req &  state0 & !state1 & !state2 & 
             !state3;

-- Node name is 'fresh_req' = ':230' 
-- Equation name is 'fresh_req', type is output 
 fresh_req = TFFE( _EQ002, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ002 =  fresh_cycle &  fresh_req &  state0 &  state1 & !state2 & !state3
         #  fresh_cycle &  fresh_req &  state0 & !state1 &  state2 & !state3
         # !fresh_cycle & !fresh_req &  state0 & !state1 &  state2 & !state3
         # !fresh_cycle & !fresh_req &  state0 &  state1 & !state2 & !state3
         #  fresh_req &  sdram_en2 & !state0 & !state1 & !state2 & !state3;

-- Node name is 'load_req' = ':192' 
-- Equation name is 'load_req', type is output 
 load_req = TFFE( _EQ003, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ003 =  load_cycle &  load_req &  state0 &  state1 &  state2 & !state3
         # !load_cycle & !load_req &  state0 &  state1 &  state2 & !state3
         #  load_req &  sdram_en2 & !state0 & !state1 & !state2 & !state3;

-- Node name is ':17' = 'sdram_en1' 
-- Equation name is 'sdram_en1', location is LC025, type is buried.
sdram_en1 = DFFE( sdram_en $  GND, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);

-- Node name is ':19' = 'sdram_en2' 
-- Equation name is 'sdram_en2', location is LC024, type is buried.
sdram_en2 = DFFE( sdram_en1 $  GND, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);

-- Node name is 'sdram_setup' = ':252' 
-- Equation name is 'sdram_setup', type is output 
 sdram_setup = DFFE( _EQ004 $  GND, GLOBAL( clk),  VCC,  VCC,  rst_l);
  _EQ004 = !sdram_en2 &  sdram_setup & !state0 & !state1 & !state2 & !state3
         #  sdram_setup & !state0 & !state1 &  state2 & !state3
         # !state0 & !state1 & !state2 &  state3
         #  sdram_setup &  state0 & !state3;

-- Node name is ':176' = 'state0' 
-- Equation name is 'state0', location is LC029, type is buried.
state0   = DFFE( _EQ005 $  GND, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ005 = !load_cycle &  state0 &  state1 &  state2 & !state3
         # !fresh_cycle &  state0 &  state1 & !state2 & !state3
         # !fresh_cycle & !state0 & !state1 &  state2 & !state3
         #  sdram_en2 & !state0 & !state1 & !state2 & !state3
         #  state0 & !state1 & !state3;

-- Node name is ':175' = 'state1' 
-- Equation name is 'state1', location is LC023, type is buried.
state1   = DFFE( _EQ006 $  GND, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ006 = !load_cycle &  state0 &  state1 &  state2 & !state3
         #  fresh_cycle &  state0 & !state1 &  state2 & !state3
         # !fresh_cycle &  state0 &  state1 & !state2 & !state3
         #  charge_cycle &  state0 & !state1 & !state2 & !state3;

-- Node name is ':174' = 'state2' 
-- Equation name is 'state2', location is LC022, type is buried.
state2   = DFFE( _EQ007 $  GND, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ007 = !load_cycle &  state0 &  state1 &  state2 & !state3
         #  fresh_cycle &  state0 &  state1 & !state2 & !state3
         # !state1 &  state2 & !state3;

-- Node name is ':173' = 'state3' 
-- Equation name is 'state3', location is LC021, type is buried.
state3   = DFFE( _EQ008 $  GND, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ008 =  load_cycle &  state0 &  state1 &  state2 & !state3
         # !state0 & !state1 & !state2 &  state3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                    d:\newsdram\sd_cnfg.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,046K