📄 sd_top.rpt
字号:
46 - - - 17 INPUT 0 0 0 1 add21
142 - - - 23 INPUT 0 0 0 1 add22
130 - - - 14 INPUT 0 0 0 1 add23
47 - - - 16 INPUT 0 0 0 1 add24
125 - - - -- INPUT 0 0 0 1 byte_en0
8 - - A -- INPUT 0 0 0 1 byte_en1
62 - - - 11 INPUT 0 0 0 1 byte_en2
12 - - A -- INPUT 0 0 0 1 byte_en3
116 - - - 05 INPUT 0 0 0 1 byte_en4
114 - - - 04 INPUT 0 0 0 1 byte_en5
64 - - - 10 INPUT 0 0 0 1 byte_en6
72 - - - 04 INPUT 0 0 0 1 byte_en7
67 - - - 08 INPUT 0 0 0 1 byte_en8
11 - - A -- INPUT 0 0 0 1 byte_en9
14 - - A -- INPUT 0 0 0 1 byte_en10
13 - - A -- INPUT 0 0 0 1 byte_en11
109 - - - 01 INPUT 0 0 0 1 byte_en12
101 - - A -- INPUT 0 0 0 1 byte_en13
7 - - A -- INPUT 0 0 0 1 byte_en14
111 - - - 02 INPUT 0 0 0 1 byte_en15
55 - - - -- INPUT G 0 0 0 0 clk
126 - - - -- INPUT 0 0 0 3 data_req
18 - - B -- INPUT 0 0 0 1 rs_ready
54 - - - -- INPUT G 0 0 0 1 rst_l
124 - - - -- INPUT 0 0 0 1 sdram_en
56 - - - -- INPUT 0 0 0 17 wr_l
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
91 - - B -- OUTPUT 0 1 0 0 data_cycle
144 - - - 24 OUTPUT 0 1 0 0 sd_add0
29 - - C -- OUTPUT 0 1 0 0 sd_add1
31 - - C -- OUTPUT 0 1 0 0 sd_add2
39 - - - 21 OUTPUT 0 1 0 0 sd_add3
27 - - C -- OUTPUT 0 1 0 0 sd_add4
33 - - C -- OUTPUT 0 1 0 0 sd_add5
30 - - C -- OUTPUT 0 1 0 0 sd_add6
137 - - - 19 OUTPUT 0 1 0 0 sd_add7
37 - - - 23 OUTPUT 0 1 0 0 sd_add8
28 - - C -- OUTPUT 0 1 0 0 sd_add9
136 - - - 19 OUTPUT 0 1 0 0 sd_add10
118 - - - 07 OUTPUT 0 0 0 0 sd_add11
21 - - B -- OUTPUT 0 1 0 0 sd_ba0
20 - - B -- OUTPUT 0 1 0 0 sd_ba1
131 - - - 15 OUTPUT 0 1 0 0 sd_cas_l
32 - - C -- OUTPUT 0 1 0 0 sd_cke
22 - - B -- OUTPUT 0 1 0 0 sd_cs0_l
122 - - - 12 OUTPUT 0 1 0 0 sd_dqm0
97 - - A -- OUTPUT 0 1 0 0 sd_dqm1
100 - - A -- OUTPUT 0 1 0 0 sd_dqm2
63 - - - 11 OUTPUT 0 1 0 0 sd_dqm3
102 - - A -- OUTPUT 0 1 0 0 sd_dqm4
98 - - A -- OUTPUT 0 1 0 0 sd_dqm5
9 - - A -- OUTPUT 0 1 0 0 sd_dqm6
10 - - A -- OUTPUT 0 1 0 0 sd_dqm7
65 - - - 09 OUTPUT 0 1 0 0 sd_dqm8
99 - - A -- OUTPUT 0 1 0 0 sd_dqm9
59 - - - 12 OUTPUT 0 1 0 0 sd_dqm10
96 - - A -- OUTPUT 0 1 0 0 sd_dqm11
95 - - A -- OUTPUT 0 1 0 0 sd_dqm12
60 - - - 12 OUTPUT 0 1 0 0 sd_dqm13
120 - - - 09 OUTPUT 0 1 0 0 sd_dqm14
121 - - - 10 OUTPUT 0 1 0 0 sd_dqm15
41 - - - 20 OUTPUT 0 1 0 0 sdram_setup
133 - - - 17 OUTPUT 0 1 0 0 sd_ras_l
17 - - B -- OUTPUT 0 1 0 0 sd_we_l
23 - - B -- OUTPUT 0 1 0 0 state_cntr0
132 - - - 16 OUTPUT 0 1 0 0 state_cntr1
19 - - B -- OUTPUT 0 1 0 0 state_cntr2
42 - - - 19 OUTPUT 0 1 0 0 state_cntr3
87 - - B -- OUTPUT 0 1 0 0 state_cntr4
86 - - B -- OUTPUT 0 1 0 0 state_cntr5
89 - - B -- OUTPUT 0 1 0 0 state_cntr6
90 - - B -- OUTPUT 0 1 0 0 state_cntr7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 13 OR2 ! 0 4 0 5 |sd_cnfg:u1|:11
- 1 - B 08 DFFE + 1 0 0 1 |sd_cnfg:u1|sdram_en1 (|sd_cnfg:u1|:17)
- 2 - B 08 DFFE + 0 1 0 5 |sd_cnfg:u1|sdram_en2 (|sd_cnfg:u1|:19)
- 3 - B 14 AND2 0 2 0 1 |sd_cnfg:u1|:36
- 4 - B 13 AND2 0 4 0 5 |sd_cnfg:u1|:37
- 2 - B 13 AND2 0 4 0 6 |sd_cnfg:u1|:59
- 5 - B 13 AND2 0 4 0 3 |sd_cnfg:u1|:81
- 1 - B 13 AND2 0 4 0 5 |sd_cnfg:u1|:104
- 8 - B 13 OR2 ! 0 4 0 4 |sd_cnfg:u1|:126
- 7 - B 13 AND2 0 4 0 2 |sd_cnfg:u1|:148
- 2 - B 24 OR2 s 0 2 0 2 |sd_cnfg:u1|~169~1
- 4 - B 14 OR2 s 0 3 0 1 |sd_cnfg:u1|~170~1
- 6 - B 24 OR2 s 0 3 0 1 |sd_cnfg:u1|~171~1
- 6 - B 13 DFFE + 0 3 0 7 |sd_cnfg:u1|state3 (|sd_cnfg:u1|:173)
- 1 - B 24 DFFE + 0 4 0 7 |sd_cnfg:u1|state2 (|sd_cnfg:u1|:174)
- 7 - B 24 DFFE + 0 4 0 7 |sd_cnfg:u1|state1 (|sd_cnfg:u1|:175)
- 5 - B 24 DFFE + 0 4 0 7 |sd_cnfg:u1|state0 (|sd_cnfg:u1|:176)
- 6 - B 15 AND2 0 2 0 3 |sd_cnfg:u1|:186
- 2 - B 14 OR2 s 0 3 0 1 |sd_cnfg:u1|~190~1
- 8 - B 21 DFFE + 0 2 0 2 |sd_cnfg:u1|:192
- 3 - B 16 OR2 s 0 3 0 1 |sd_cnfg:u1|~206~1
- 4 - B 16 DFFE + 0 3 0 3 |sd_cnfg:u1|:208
- 1 - B 14 OR2 s 0 4 0 1 |sd_cnfg:u1|~228~1
- 5 - B 14 OR2 s 0 2 0 1 |sd_cnfg:u1|~228~2
- 6 - B 14 DFFE + 0 3 0 1 |sd_cnfg:u1|:230
- 7 - B 14 OR2 s 0 4 0 1 |sd_cnfg:u1|~250~1
- 8 - B 14 OR2 s 0 4 0 1 |sd_cnfg:u1|~250~2
- 1 - B 20 DFFE + 1 2 1 0 |sd_cnfg:u1|:252
- 2 - B 22 AND2 0 3 0 3 |sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:87
- 1 - B 23 AND2 0 3 0 3 |sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:95
- 2 - B 23 AND2 0 2 0 3 |sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:99
- 1 - B 18 AND2 0 3 0 3 |sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:107
- 2 - B 18 AND2 0 2 0 1 |sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|:111
- 3 - B 18 DFFE + 0 3 0 1 |sd_rfrsh:u3|rfrsh_cntr10 (|sd_rfrsh:u3|:42)
- 4 - B 18 DFFE + 0 3 0 2 |sd_rfrsh:u3|rfrsh_cntr9 (|sd_rfrsh:u3|:43)
- 7 - B 18 DFFE + 0 2 0 3 |sd_rfrsh:u3|rfrsh_cntr8 (|sd_rfrsh:u3|:44)
- 5 - B 18 DFFE + 0 3 0 2 |sd_rfrsh:u3|rfrsh_cntr7 (|sd_rfrsh:u3|:45)
- 8 - B 18 DFFE + 0 2 0 3 |sd_rfrsh:u3|rfrsh_cntr6 (|sd_rfrsh:u3|:46)
- 3 - B 23 DFFE + 0 2 0 2 |sd_rfrsh:u3|rfrsh_cntr5 (|sd_rfrsh:u3|:47)
- 6 - B 23 DFFE + 0 3 0 1 |sd_rfrsh:u3|rfrsh_cntr4 (|sd_rfrsh:u3|:48)
- 5 - B 23 DFFE + 0 2 0 2 |sd_rfrsh:u3|rfrsh_cntr3 (|sd_rfrsh:u3|:49)
- 7 - B 22 DFFE + 0 3 0 1 |sd_rfrsh:u3|rfrsh_cntr2 (|sd_rfrsh:u3|:50)
- 1 - B 22 DFFE + 0 2 0 2 |sd_rfrsh:u3|rfrsh_cntr1 (|sd_rfrsh:u3|:51)
- 5 - B 22 DFFE + 0 1 0 3 |sd_rfrsh:u3|rfrsh_cntr0 (|sd_rfrsh:u3|:52)
- 6 - B 18 AND2 s 0 3 0 1 |sd_rfrsh:u3|~53~1
- 7 - B 23 AND2 s 0 4 0 1 |sd_rfrsh:u3|~53~2
- 8 - B 23 DFFE + 0 3 0 1 |sd_rfrsh:u3|:72
- 4 - B 10 DFFE + 0 2 1 4 |sd_sig:u4|:119
- 5 - B 10 DFFE + 0 2 1 1 |sd_sig:u4|:120
- 7 - B 10 DFFE + 0 2 1 1 |sd_sig:u4|:121
- 7 - B 19 DFFE + 0 2 1 1 |sd_sig:u4|:122
- 1 - B 19 DFFE + 0 2 1 4 |sd_sig:u4|:123
- 3 - B 15 DFFE + 0 2 1 1 |sd_sig:u4|:124
- 8 - B 15 DFFE + 0 2 1 1 |sd_sig:u4|:125
- 7 - B 15 DFFE + 0 1 1 10 |sd_sig:u4|:126
- 4 - B 19 AND2 1 1 0 1 |sd_sig:u4|:230
- 7 - C 21 AND2 1 1 0 1 |sd_sig:u4|:231
- 4 - C 21 AND2 1 1 0 1 |sd_sig:u4|:232
- 3 - C 21 AND2 1 1 0 1 |sd_sig:u4|:233
- 1 - C 21 AND2 1 1 0 1 |sd_sig:u4|:234
- 7 - C 24 AND2 1 1 0 1 |sd_sig:u4|:235
- 5 - C 24 AND2 1 1 0 1 |sd_sig:u4|:236
- 3 - C 24 AND2 1 1 0 1 |sd_sig:u4|:237
- 2 - B 19 AND2 0 3 0 10 |sd_sig:u4|:355
- 5 - B 19 DFFE + ! 1 3 1 0 |sd_sig:u4|:403
- 2 - C 24 DFFE + 1 3 1 0 |sd_sig:u4|:404
- 8 - C 24 DFFE + 1 3 1 0 |sd_sig:u4|:405
- 3 - B 19 DFFE + 1 3 1 0 |sd_sig:u4|:406
- 5 - C 21 DFFE + 1 3 1 0 |sd_sig:u4|:407
- 8 - C 21 DFFE + 1 3 1 0 |sd_sig:u4|:408
- 2 - C 21 DFFE + 1 3 1 0 |sd_sig:u4|:409
- 6 - C 21 DFFE + 1 3 1 0 |sd_sig:u4|:410
- 6 - C 24 DFFE + 1 3 1 0 |sd_sig:u4|:411
- 4 - C 24 DFFE + 1 3 1 0 |sd_sig:u4|:412
- 1 - C 24 DFFE + 1 3 1 0 |sd_sig:u4|:413
- 2 - B 15 OR2 ! 0 2 0 11 |sd_sig:u4|:414
- 8 - B 17 AND2 0 2 0 11 |sd_sig:u4|:418
- 8 - B 19 AND2 0 2 0 1 |sd_sig:u4|:422
- 6 - B 19 OR2 s 0 4 0 2 |sd_sig:u4|~451~1
- 4 - B 15 DFFE + 1 3 1 0 |sd_sig:u4|:455
- 5 - B 15 DFFE + 1 3 1 0 |sd_sig:u4|:456
- 6 - B 17 DFFE + ! 0 4 1 0 |sd_sig:u4|:478
- 4 - B 17 DFFE + ! 0 4 1 0 |sd_sig:u4|:500
- 1 - B 05 AND2 1 1 0 18 |sd_sig:u4|:504
- 1 - B 15 DFFE + ! 0 4 1 0 |sd_sig:u4|:517
- 7 - B 17 AND2 s 0 2 0 5 |sd_sig:u4|~533~1
- 1 - B 17 DFFE + ! 1 3 1 0 |sd_sig:u4|:536
- 7 - C 19 DFFE + 0 0 1 0 |sd_sig:u4|:538
- 2 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:592
- 5 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:593
- 6 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:594
- 8 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:595
- 7 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:596
- 4 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:597
- 4 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:598
- 8 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:599
- 3 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:600
- 2 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:601
- 5 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:602
- 1 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:603
- 1 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:604
- 3 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:605
- 6 - A 10 DFFE + 2 1 1 0 |sd_sig:u4|:606
- 7 - A 12 DFFE + 2 1 1 0 |sd_sig:u4|:607
- 5 - B 17 AND2 0 4 0 3 |sd_state:u2|:20
- 8 - B 22 AND2 s 0 2 0 2 |sd_state:u2|~90~1
- 6 - B 22 AND2 s 0 2 0 3 |sd_state:u2|~92~1
- 8 - B 24 AND2 s 0 2 0 2 |sd_state:u2|~95~1
- 3 - B 24 AND2 0 4 0 2 |sd_state:u2|:95
- 2 - B 17 AND2 0 4 0 3 |sd_state:u2|:122
- 4 - B 24 AND2 0 4 0 2 |sd_state:u2|:150
- 3 - B 17 AND2 0 4 0 2 |sd_state:u2|:177
- 5 - B 16 OR2 s 1 3 0 1 |sd_state:u2|~214~1
- 6 - B 16 AND2 s ! 0 3 0 1 |sd_state:u2|~218~1
- 8 - B 16 OR2 s 0 4 0 1 |sd_state:u2|~218~2
- 1 - B 16 DFFE + 0 3 0 7 |sd_state:u2|sdram_cycle4 (|sd_state:u2|:220)
- 3 - B 22 DFFE + 0 4 0 24 |sd_state:u2|sdram_cycle3 (|sd_state:u2|:221)
- 2 - B 16 DFFE + 1 3 1 11 |sd_state:u2|sdram_cycle2 (|sd_state:u2|:222)
- 4 - B 22 DFFE + 0 4 0 10 |sd_state:u2|sdram_cycle1 (|sd_state:u2|:223)
- 7 - B 16 DFFE + ! 1 3 0 12 |sd_state:u2|sdram_cycle0 (|sd_state:u2|:224)
- 4 - B 23 AND2 ! 0 2 0 2 :93
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 12/ 96( 12%) 13/ 48( 27%) 0/ 48( 0%) 7/16( 43%) 9/16( 56%) 0/16( 0%)
B: 19/ 96( 19%) 3/ 48( 6%) 40/ 48( 83%) 3/16( 18%) 11/16( 68%) 0/16( 0%)
C: 9/ 96( 9%) 0/ 48( 0%) 17/ 48( 35%) 7/16( 43%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
11: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
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