📄 sd_top.rpt
字号:
Project Information d:\newsdram\sd_top.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/24/2008 19:56:06
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
sd_top EPF10K10TC144-3 43 45 0 0 0 % 121 21 %
User Pins: 43 45 0
Project Information d:\newsdram\sd_top.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop '|sd_sig:u4|:402' stuck at GND
Warning: Ignored unnecessary INPUT pin 'add3'
Warning: Ignored unnecessary INPUT pin 'add2'
Warning: Ignored unnecessary INPUT pin 'add1'
Warning: Ignored unnecessary INPUT pin 'add0'
Project Information d:\newsdram\sd_top.rpt
** FILE HIERARCHY **
|sd_state:u2|
|sd_cnfg:u1|
|sd_rfrsh:u3|
|sd_rfrsh:u3|lpm_add_sub:73|
|sd_rfrsh:u3|lpm_add_sub:73|addcore:adder|
|sd_rfrsh:u3|lpm_add_sub:73|altshift:result_ext_latency_ffs|
|sd_rfrsh:u3|lpm_add_sub:73|altshift:carry_ext_latency_ffs|
|sd_rfrsh:u3|lpm_add_sub:73|altshift:oflow_ext_latency_ffs|
|sd_sig:u4|
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
***** Logic for device 'sd_top' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
** ERROR SUMMARY **
Info: Chip 'sd_top' in device 'EPF10K10TC144-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
s
t
a b b
R s s t s R d b s s s R s R b b R R y R y
s E s d d e d E a y d s d d E d E y y E E t E t
d S d _ _ _ _ S G t t r V d _ _ S _ S t t S S e S e
_ a a E G a _ a a V r c c a G E N a e a C _ d d E a E e V e E E _ E _
a d d a R N d a d d C a n a d N R D _ _ m C d q q R d R _ C _ R R e R e
d d d d V D d d d d C s t s d D V I r e _ I q m m V d V e C e V V n V n
d 1 2 d E I 1 d 1 1 I _ r _ 2 I E N e n e N m 1 1 E 1 E n I n E E 1 E 1
0 0 2 8 D O 4 7 0 2 O l 1 l 3 O D T q 0 n T 0 5 4 D 1 D 4 O 5 D D 5 D 2
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
byte_en14 | 7 102 | sd_dqm4
byte_en1 | 8 101 | byte_en13
sd_dqm6 | 9 100 | sd_dqm2
sd_dqm7 | 10 99 | sd_dqm9
byte_en9 | 11 98 | sd_dqm5
byte_en3 | 12 97 | sd_dqm1
byte_en11 | 13 96 | sd_dqm11
byte_en10 | 14 95 | sd_dqm12
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
sd_we_l | 17 92 | add19
rs_ready | 18 91 | data_cycle
state_cntr2 | 19 EPF10K10TC144-3 90 | state_cntr7
sd_ba1 | 20 89 | state_cntr6
sd_ba0 | 21 88 | add11
sd_cs0_l | 22 87 | state_cntr4
state_cntr0 | 23 86 | state_cntr5
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
add20 | 26 83 | add4
sd_add4 | 27 82 | add16
sd_add9 | 28 81 | add17
sd_add1 | 29 80 | add5
sd_add6 | 30 79 | add15
sd_add2 | 31 78 | add6
sd_cke | 32 77 | ^MSEL0
sd_add5 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
add7 | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
s R s G s s R R V a a a a G a V V r c w G G s s V b s b s G b R R R V b
d E d N d t E E C d d d d N d C C s l r N N d d C y d y d N y E E E C y
_ S _ D r a S S C d d d d D d C C t k _ D D _ _ C t _ t _ D t S S S C t
a E a I a t E E I 2 2 9 1 I 1 I I _ l I I d d I e d e d I e E E E I e
d R d O m e R R O 1 4 3 O 8 N N l N N q q O _ q _ q O _ R R R O _
d V d _ _ V V T T T T m m e m e m e V V V e
8 E 3 s c E E 1 1 n 3 n 8 n E E E n
D e n D D 0 3 2 6 8 D D D 7
t t
u r
p 3
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A10 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 1/2 10/22( 45%)
A12 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 10/22( 45%)
B5 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B8 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 1/22( 4%)
B10 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
B13 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 4/22( 18%)
B14 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
B15 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 1/2 8/22( 36%)
B16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
B17 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 1/2 8/22( 36%)
B18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 2/22( 9%)
B19 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 10/22( 45%)
B20 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
B21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
B22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 6/22( 27%)
B23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
B24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 12/22( 54%)
C19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 0/22( 0%)
C21 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
C24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 82/96 ( 85%)
Total logic cells used: 121/576 ( 21%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.09/4 ( 77%)
Total fan-in: 375/2304 ( 16%)
Total input pins required: 43
Total input I/O cell registers required: 0
Total output pins required: 45
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 121
Total flipflops required: 69
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 19/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 16/0
B: 0 0 0 0 1 0 0 2 0 3 0 0 0 8 8 8 8 8 8 8 1 1 8 8 8 88/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 0 0 8 17/0
Total: 0 0 0 0 1 0 0 2 0 11 0 8 0 8 8 8 8 8 8 9 1 9 8 8 16 121/0
Device-Specific Information: d:\newsdram\sd_top.rpt
sd_top
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - C -- INPUT 0 0 0 1 add4
80 - - C -- INPUT 0 0 0 1 add5
78 - - C -- INPUT 0 0 0 1 add6
36 - - - 24 INPUT 0 0 0 1 add7
141 - - - 22 INPUT 0 0 0 1 add8
48 - - - 15 INPUT 0 0 0 1 add9
143 - - - 24 INPUT 0 0 0 1 add10
88 - - B -- INPUT 0 0 0 1 add11
135 - - - 18 INPUT 0 0 0 1 add12
49 - - - 14 INPUT 0 0 0 1 add13
138 - - - 20 INPUT 0 0 0 1 add14
79 - - C -- INPUT 0 0 0 1 add15
82 - - C -- INPUT 0 0 0 1 add16
81 - - C -- INPUT 0 0 0 1 add17
51 - - - 13 INPUT 0 0 0 1 add18
92 - - B -- INPUT 0 0 0 1 add19
26 - - C -- INPUT 0 0 0 1 add20
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -