sd_cnfg.v

8读8写SDRAM verilog 程序

`timescale 1 ns /  100 ps
module sd_cnfg(	sdram_en,
				clk,
               	rst_l,

               	load_req,
				charge_req,
				fresh_req,

				load_cycle,
				fresh_cycle,
				charge_cycle,
               	sdram_setup
			);

//---------------------------------------------------------------------
// inputs

input			sdram_en;
input			clk;
input			rst_l;

output          load_req;
output			charge_req;
output			fresh_req;

input			load_cycle;
input			fresh_cycle;
input			charge_cycle;                                   

output          sdram_setup;
//---------------------------------------------------------------------
reg				sdram_en1,
				sdram_en2;			// enable sync'd twice

reg		[3:0]	state;				// state bits

reg             sdram_setup;        // setup complete

parameter idle      = 4'b0000;
parameter precharge = 4'b0001;
parameter refresh1  = 4'b0011;
parameter nop2      = 4'b0100;
parameter refresh2  = 4'b0101;
parameter load_mode = 4'b0111;
parameter all_done  = 4'b1000;

//---------------------------------------------------------------------
// synchronize enable

always @(posedge clk or negedge rst_l)
	if (!rst_l) begin
		sdram_en1 <= #1   1'b0;
		sdram_en2 <= #1   1'b0;
		end
	else begin
		sdram_en1 <= #1   sdram_en;
		sdram_en2 <= #1   sdram_en1;
		end
		
//---------------------------------------------------------------------
// state machine
reg		load_req;
reg		charge_req;
reg		fresh_req;

always @(posedge clk or negedge rst_l)
   	if (!rst_l) begin
      	state      	<= #1   idle;
		load_req	<= #1  1'b0;
		charge_req	<= #1  1'b0;
		fresh_req	<= #1  1'b0;
	  end

   else 

	casex (state)
	idle : if (sdram_en2) begin
        state          <= #1   precharge;
		load_req	<= #1  1'b0;
		charge_req	<= #1  1'b0;
		fresh_req	<= #1  1'b0;
		sdram_setup    <= #1   1'b0;
	    end

	precharge : 
		if (charge_cycle) begin
	  		state          <= #1   refresh1;
			charge_req<= #1  1'b0;
	    end
		else
			charge_req<= #1  1'b1;

	refresh1 : 
		if (fresh_cycle) begin
	  		state          	<= #1   nop2;
			fresh_req		<= #1  1'b0;
	    end
		else
			fresh_req		<= #1  1'b1;
	  
	nop2 : begin
		if(!fresh_cycle)
			state          <= #1   refresh2;
	    end
	refresh2 : 
		if (fresh_cycle) begin
	  		state 		<= #1   load_mode;
			fresh_req	<= #1  1'b0;
	    end
		else
			fresh_req<= #1  1'b1;

	load_mode : 
		if (load_cycle) begin
			load_req<= #1  1'b0;
	  		state    	<= #1   all_done;
	    end	  
		else
			load_req<= #1  1'b1;
	all_done : begin
		state          <= #1   all_done;
		sdram_setup    <= #1   1'b1;
	end
	default : begin
      	state          <= #1   idle;
	  	sdram_setup    <= #1   1'b0;
	    end
	endcase

endmodule