sd_rfrsh.v

来自「8读8写SDRAM verilog 程序」· Verilog 代码 · 共 54 行

`timescale 1 ns /  100 ps

module sd_rfrsh(  clk,
                  rst_l,
                  fresh_cycle,
                  fresh_req);
                  
//---------------------------------------------------------------------
// port list
input          	clk;
input          	rst_l;
input  		   	fresh_cycle;

output         	fresh_req;
//---------------------------------------------------------------------
reg            	fresh_req;
reg   [10:0]   	rfrsh_cntr;

//---------------------------------------------------------------------
// parameters -- set count to desired clock frequency
/*
parameter cnt_110 = 1738;              // 110 Mhz clock
parameter cnt_80 = 1264;               // 80 Mhz clock
parameter cnt_66 = 1053;               // 66 Mhz clock
parameter cnt_50 = 790;                // 50 Mhz clock
parameter cnt_40 = 632;                // 40 Mhz clock
parameter cnt_33 = 526;                // 33 Mhz clock
parameter count = cnt_66;              // set for 66 mhz
*/
//---------------------------------------------------------------------
always @(posedge clk or negedge rst_l)
   if (!rst_l)
      rfrsh_cntr <= #1 11'b0;
   else 
		if (fresh_cycle)
      		rfrsh_cntr <= #1 11'd0;
   		else
      		rfrsh_cntr <= #1 rfrsh_cntr + 11'd1; 
//---------------------------------------------------------------------
always @(posedge clk or negedge rst_l)
	if (!rst_l)
      	fresh_req <= #1 1'b0;
   	else
		if(fresh_cycle)
			fresh_req<= #1 1'b0;
		else 
//			if (rfrsh_cntr == count) 
			if (rfrsh_cntr == 127) 
    			  fresh_req <= #1 1'b1;
			else
					fresh_req<=fresh_req;
endmodule