post_norm_arch.vhd

使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。

    -- Fasu Output will be denormalized ...
    dn <= NOT op_mul AND NOT op_div AND
        (exp_in_00 OR (exp_next_mi(8) AND NOT fract_in(47)) );

    ---------------------------------------------------------------------------
    -- Fraction Normalization
    ---------------------------------------------------------------------------
    
    -- Incremented fraction for rounding
    fract_out_pl1 <= ('0' & fract_out) + '1';

    -- Special Signals for f2i
    f2i_emin <= X"7e" WHEN (rmode_00 = '1') ELSE X"7f";
    f2i_zero <= '1' WHEN (((opas = '0') AND (exp_in < f2i_emin)) OR
                          ((opas = '1') AND (exp_in > f2i_emax)) OR
                          ((opas = '1') AND (exp_in < f2i_emin) AND
                           ((fract_in_00 OR NOT rmode_11) = '1')))
                ELSE '0';
    f2i_max <= '1' WHEN (((opas = '0') AND (exp_in > f2i_emax)) OR
                         ((opas = '1') AND (exp_in < f2i_emin) AND
                          (fract_in_00 = '0') AND (rmode_11 = '1')))
               ELSE '0';
    
    -- Claculate various shifting options

    shftr_mul <= exp_out WHEN ((NOT exp_ovf(1) AND exp_in_00) ='1')
                 else exp_in_mi1(7 DOWNTO 0) ;
    shft_co <= '0' WHEN ((NOT exp_ovf(1) AND exp_in_00) ='1') else exp_in_mi1(8) ;
    
    div_shft1 <= ("000" & div_opa_ldz) WHEN (exp_in_00 = '1') ELSE
                 div_scht1a(7 DOWNTO 0);
    div_shft1_co <= '0' WHEN (exp_in_00 = '1') ELSE
                    div_scht1a(8);
    
    div_scht1a <= ('0' & exp_in) - div_opa_ldz; -- 9 bits - includes carry out
    div_shft2 <= exp_in + "10";
    div_shft3 <= div_opa_ldz+exp_in;
    div_shft4 <= div_opa_ldz-exp_in;

    div_dn <= op_dn and div_shft1_co;
    div_nr <= '1' WHEN ((op_dn = '1') and (exp_ovf(1) = '1') and
                        (or_reduce(fract_in(46 DOWNTO 23)) = '0') AND
                        (div_shft3 > X"16")) ELSE
              '0';

    f2i_shft <= exp_in - X"7d";

    -- Select shifting direction
    left_right <= lr_div WHEN (op_div ='1') ELSE
                  lr_mul WHEN (op_mul = '1') ELSE
                  '1';

                                                               
    lr_div <= '1' WHEN ((op_dn AND NOT exp_ovf(1) AND  exp_ovf(0)) = '1') ELSE 
              '0' WHEN ((op_dn AND exp_ovf(1)) = '1') ELSE 
              '0' WHEN ((op_dn AND div_shft1_co) = '1') ELSE 
              '1' WHEN ((op_dn AND exp_out_00) = '1') ELSE 
              '1' WHEN ((NOT op_dn AND  exp_out_00 AND NOT exp_ovf(1)) = '1') ELSE 
              '0' WHEN ((exp_ovf(1)) = '1') ELSE
              '1';

    lr_mul <= '1' WHEN ((shft_co OR (NOT exp_ovf(1) AND exp_in_00) OR 
                         (NOT exp_ovf(1) AND NOT exp_in_00 AND
                          (exp_out1_co OR exp_out_00) )) = '1') ELSE 
              '0' WHEN (( exp_ovf(1) or exp_in_00 ) = '1') ELSE
              '1';

    -- Select Left and Right shift value
    fasu_shift_p1 <= X"02" WHEN (exp_in_00 = '1') ELSE exp_in_pl1(7 downto 0);
    fasu_shift <= fasu_shift_p1 WHEN ((dn OR exp_out_00) = '1') ELSE ("00" & fi_ldz);

    shift_right <= shftr_div WHEN (op_div = '1') ELSE shftr_mul;

    conv_shft <= f2i_shft WHEN (op_f2i = '1') ELSE ("00" & fi_ldz);

    shift_left <= shftl_div WHEN (op_div = '1') ELSE
                  shftl_mul WHEN (op_mul = '1') ELSE
                  conv_shft WHEN ((op_f2i or op_i2f) = '1') else
                  fasu_shift;

    shftl_mul <= exp_in_pl1(7 DOWNTO 0) WHEN
                 ((shft_co OR (NOT exp_ovf(1) AND  exp_in_00) OR 
                   (NOT exp_ovf(1) AND  NOT exp_in_00 AND 
                    (exp_out1_co OR exp_out_00))) = '1') ELSE
                 ("00" & fi_ldz);

    shftl_div <= div_shft1(7 downto 0) WHEN
                 ((op_dn and exp_out_00 and
                   not (not exp_ovf(1) and exp_ovf(0))) ='1') else
                 exp_in(7 downto 0) WHEN
                 ((not op_dn and exp_out_00 and not exp_ovf(1))='1') else
                 ("00" & fi_ldz);
    
    shftr_div <= div_shft3 WHEN ((op_dn AND exp_ovf(1)) = '1') else
                 div_shft4 WHEN ((op_dn AND div_shft1_co) = '1') else
                 div_shft2;

    -- Do the actual shifting
    fract_in_shftr <= (OTHERS => '0') WHEN (or_reduce(shift_right(7 DOWNTO 6)) = '1') else
                      shr(fract_in,shift_right(5 DOWNTO 0));

    fract_in_shftl <= (OTHERS => '0') WHEN
                      ((or_reduce(shift_left(7 DOWNTO 6))='1') OR
                       ((f2i_zero AND op_f2i)='1')) else
                      (SHL(fract_in,shift_left(5 DOWNTO 0)));

    -- Chose final fraction output
    fract_trunc <= fract_in_shftl(24 DOWNTO 0) WHEN (left_right = '1') else
                   fract_in_shftr(24 DOWNTO 0);
    fract_out <= fract_in_shftl(47 DOWNTO 25) WHEN (left_right = '1') else
                 fract_in_shftr(47 DOWNTO 25);
    ---------------------------------------------------------------------------
    --  Exponent Normalization
    ---------------------------------------------------------------------------
    fi_ldz_mi1 <= fi_ldz - '1';
    fi_ldz_mi22 <= fi_ldz - "10110";
    exp_out_pl1 <= exp_out + '1';
    exp_out_mi1 <= exp_out - '1';
    -- 9 bits - includes carry out
    exp_in_pl1 <= ('0' & exp_in)  + '1';
    -- 9 bits - includes carry out
    exp_in_mi1 <= ('0' & exp_in)  - '1';     
    exp_out1_mi1 <= exp_out1 - '1';
    
    -- 9 bits - includes carry out
    exp_next_mi <= exp_in_pl1 - fi_ldz_mi1; 

    exp_fix_diva <= exp_in - fi_ldz_mi22;
    exp_fix_divb <= exp_in - fi_ldz_mi1;

    exp_zero  <= (exp_ovf(1) AND NOT exp_ovf(0) AND op_mul AND
                  (NOT exp_rnd_adj2a OR NOT rmode(1))) OR
                 (op_mul AND  exp_out1_co);

    exp_out1 <= exp_in_pl1(7 DOWNTO 0) WHEN (fract_in(47) = '1') else
                exp_next_mi(7 DOWNTO 0);
    exp_out1_co <= exp_in_pl1(8) WHEN (fract_in(47) = '1') else
                   exp_next_mi(8);

    f2i_out_sign <=  f2i_out_sign_p1 WHEN (opas ='0') ELSE
                     f2i_out_sign_p2;

    f2i_out_sign_p1 <= '0' WHEN (exp_in<f2i_emin) ELSE
                       '0' WHEN (exp_in>f2i_emax) ELSE
                       opas;
                               
    f2i_out_sign_p2 <= '0' WHEN (exp_in<f2i_emin) ELSE
                       '1'WHEN (exp_in>f2i_emax) ELSE
                       opas;
    
    exp_i2f   <= X"9e" WHEN ((fract_in_00 AND opas)='1') else 
                 X"00" WHEN ((fract_in_00 AND NOT opas)='1') else 
                 (X"9e"-fi_ldz);

    exp_f2i_1 <= shl((fract_in(47) & fract_in(47) & fract_in(47) & fract_in(47) &
                      fract_in(47) & fract_in(47) & fract_in(47) & fract_in(47) &
                      fract_in),f2i_shft);
    
    exp_f2i   <= (OTHERS => '0') WHEN (f2i_zero = '1') else
                 X"ff" WHEN (f2i_max = '1') else
                 exp_f2i_1(55 DOWNTO 48);
    conv_exp  <= exp_f2i WHEN (op_f2i = '1') ELSE exp_i2f;

    exp_out <= exp_div WHEN (op_div = '1') ELSE
               conv_exp WHEN ((op_f2i OR op_i2f)='1') ELSE
               X"00" WHEN (exp_zero = '1') ELSE
               ("000000" & fract_in(47 downto 46)) WHEN (dn = '1') else
               exp_out1;

    ldz_all <= ("00" & div_opa_ldz) + fi_ldz;
    ldz_dif <= fi_ldz_2 - div_opa_ldz;
    fi_ldz_2a <= "0010111" - fi_ldz;
    fi_ldz_2 <= (fi_ldz_2a(6) & fi_ldz_2a(6 DOWNTO 0));

    -- 9 bits - includes carry out
    div_exp1 <= exp_in_mi1 + fi_ldz_2;       

    div_exp2_temp <= exp_in_pl1 - ldz_all;
    div_exp2 <= div_exp2_temp(7 DOWNTO 0);
    div_exp3 <= exp_in + ldz_dif;
    
    exp_div <= div_exp3 when ((opa_dn AND opb_dn) = '1') ELSE 
               div_exp1(7 DOWNTO 0) WHEN (opb_dn = '1') ELSE 
               div_exp2 WHEN ((opa_dn = '1') AND
                              NOT ( (exp_in<div_opa_ldz) OR (div_exp2>"011111110") )) ELSE 
               (OTHERS => '0') WHEN ((opa_dn or (exp_in_00 and NOT exp_ovf(1)) ) = '1') ELSE 
               exp_out1_mi1;

    div_inf <= '1' WHEN ((opb_dn = '1') AND  (opa_dn = '0') and
                         (div_exp1(7 DOWNTO 0) < X"7f"))
               ELSE '0';

    ---------------------------------------------------------------------------
    -- ROUND
    ---------------------------------------------------------------------------
    -- Extract rounding (GRS) bits
    grs_sel_div <= op_div and (exp_ovf(1) or div_dn or exp_out1_co or exp_out_00);

    g <= fract_out(0) WHEN (grs_sel_div = '1') ELSE fract_out(0);
    r <= (fract_trunc(24) AND NOT div_nr) WHEN (grs_sel_div = '1') ELSE fract_trunc(24);
    s <= or_reduce(fract_trunc(24 DOWNTO 0)) WHEN (grs_sel_div = '1') ELSE
         (or_reduce(fract_trunc(23 DOWNTO 0)) OR (fract_trunc(24) AND op_div));

    -- Round to nearest even
    round <= (g and r) or (r and s) ;
    fract_out_rnd0 <= fract_out_pl1(22 DOWNTO 0) WHEN (round = '1') ELSE fract_out;
    exp_rnd_adj0 <= fract_out_pl1(23) WHEN (round = '1') ELSE '0';

    exp_out_rnd0 <=  exp_out_pl1 WHEN (exp_rnd_adj0 = '1') else exp_out;
    ovf0 <= exp_out_final_ff and NOT rmode_01 AND NOT op_f2i;

    -- round to zero
    fract_out_rnd1 <= ("111" & X"fffff") WHEN
                      ((exp_out_ff and NOT op_div AND
                        NOT dn and NOT op_f2i) = '1')
                      ELSE fract_out;
    exp_fix_div <= exp_fix_diva  WHEN (fi_ldz>"010110")
                   else exp_fix_divb;
    exp_out_rnd1 <= exp_fix_div WHEN ((g and r and s and exp_in_ff AND op_div)='1') else
                    exp_next_mi(7 DOWNTO 0) WHEN ((g and r and s and exp_in_ff AND NOT op_div)='1') else
                    exp_in when ((exp_out_ff and not op_f2i)='1') else
                    exp_out;        
    ovf1 <= exp_out_ff and NOT dn;

    -- round to +inf (UP) and -inf (DOWN)
    r_sign <= sign;

    round2a <= NOT exp_out_fe or NOT fract_out_7fffff or
               (exp_out_fe and fract_out_7fffff);
    round2_fasu <= ((r or s) and NOT r_sign) and