post_norm_arch.vhd

使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_misc.ALL;

ENTITY post_norm IS
   PORT( 
      clk          : IN     std_logic  ;
      div_opa_ldz  : IN     std_logic_vector (4 downto 0) ;
      exp_in       : IN     std_logic_vector (7 downto 0) ;
      exp_ovf      : IN     std_logic_vector (1 downto 0) ;
      fpu_op       : IN     std_logic_vector (2 downto 0) ;
      fract_in     : IN     std_logic_vector (47 downto 0) ;
      opa_dn       : IN     std_logic  ;
      opas         : IN     std_logic  ;
      opb_dn       : IN     std_logic  ;
      output_zero  : IN     std_logic  ;
      rem_00       : IN     std_logic  ;
      rmode        : IN     std_logic_vector (1 downto 0) ;
      sign         : IN     std_logic  ;
      f2i_out_sign : OUT    std_logic  ;
      fpout        : OUT    std_logic_vector (30 downto 0) ;
      ine          : OUT    std_logic  ;
      overflow     : OUT    std_logic  ;
      underflow    : OUT    std_logic 
   );
END post_norm ;

ARCHITECTURE arch OF post_norm IS
    signal f2i_out_sign_p1,  f2i_out_sign_p2: std_logic;
    signal fract_out : std_logic_vector (22 downto 0);
    signal exp_out : std_logic_vector (7 downto 0);
    signal exp_out1_co : std_logic ;
    signal fract_out_final : std_logic_vector (22 downto 0);
    signal fract_out_rnd : std_logic_vector (22 downto 0);
    signal exp_next_mi : std_logic_vector (8 downto 0);
    signal dn : std_logic ;
    signal exp_rnd_adj : std_logic ;
    signal exp_out_final : std_logic_vector (7 downto 0);
    signal exp_out_rnd : std_logic_vector (7 downto 0);
    signal op_dn : std_logic ;
    signal op_mul : std_logic ;
    signal op_div : std_logic ;
    signal op_i2f : std_logic ;
    signal op_f2i : std_logic ;
    signal fi_ldz : std_logic_vector (5 downto 0);
    signal g, r, s : std_logic ;
    signal round, round2, round2a, round2_fasu, round2_fmul : std_logic ;
    signal exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a : std_logic_vector (7 downto 0);
    signal fract_out_rnd0, fract_out_rnd1, fract_out_rnd2, fract_out_rnd2a : std_logic_vector (22 downto 0);
    signal exp_rnd_adj0, exp_rnd_adj2a : std_logic ;
    signal r_sign : std_logic ;
    signal ovf0, ovf1 : std_logic ;
    signal fract_out_pl1 : std_logic_vector (23 downto 0);
    signal exp_out_pl1, exp_out_mi1 : std_logic_vector (7 downto 0);
    signal exp_out_00, exp_out_fe, exp_out_ff, exp_in_00, exp_in_ff : std_logic ;
    signal exp_out_final_ff, fract_out_7fffff : std_logic ;
    signal fract_trunc : std_logic_vector (24 downto 0);
    signal exp_out1 : std_logic_vector (7 downto 0);
    signal grs_sel : std_logic ;
    signal fract_out_00, fract_in_00 : std_logic ;
    signal shft_co : std_logic ;
    signal exp_in_pl1, exp_in_mi1 : std_logic_vector (8 downto 0);
    signal fract_in_shftr : std_logic_vector (47 downto 0);
    signal fract_in_shftl : std_logic_vector (47 downto 0);
    signal exp_div : std_logic_vector (7 downto 0);
    signal shft2 : std_logic_vector (7 downto 0);
    signal exp_out1_mi1 : std_logic_vector (7 downto 0);
    signal div_dn : std_logic ;
    signal div_nr : std_logic ;
    signal grs_sel_div : std_logic ;
    signal div_inf : std_logic ;
    signal fi_ldz_2a : std_logic_vector (6 downto 0);
    signal fi_ldz_2 : std_logic_vector (7 downto 0);
    signal div_shft1, div_shft2, div_shft3, div_shft4 : std_logic_vector (7 downto 0);
    signal div_shft1_co : std_logic ;
    signal div_exp1 : std_logic_vector (8 downto 0);
    signal div_exp2, div_exp3 : std_logic_vector (7 downto 0);
    signal div_exp2_temp : std_logic_vector (8 downto 0);
    signal left_right, lr_mul, lr_div : std_logic ;
    signal shift_right, shftr_mul, shftr_div : std_logic_vector (7 downto 0);
    signal shift_left, shftl_mul, shftl_div : std_logic_vector (7 downto 0);
    signal fasu_shift_p1 : std_logic_vector (7 downto 0);
    signal fasu_shift : std_logic_vector (7 downto 0);
    signal exp_fix_div : std_logic_vector (7 downto 0);
    signal exp_fix_diva, exp_fix_divb : std_logic_vector (7 downto 0);
    signal fi_ldz_mi1 : std_logic_vector (5 downto 0);
    signal fi_ldz_mi22 : std_logic_vector (5 downto 0);
    signal exp_zero : std_logic ;
    signal ldz_all : std_logic_vector (6 downto 0);
    signal ldz_dif : std_logic_vector (7 downto 0);
    signal div_scht1a : std_logic_vector (8 downto 0);
    signal f2i_shft : std_logic_vector (7 downto 0);
    signal exp_f2i_1 : std_logic_vector (55 downto 0);
    signal f2i_zero, f2i_max : std_logic ;
    signal f2i_emin : std_logic_vector (7 downto 0);
    signal conv_shft : std_logic_vector (7 downto 0);
    signal exp_i2f, exp_f2i, conv_exp : std_logic_vector (7 downto 0);
    signal round2_f2i : std_logic ;
    signal round2_f2i_p1 : std_logic ;
    signal exp_in_80 : std_logic ;
    signal rmode_00, rmode_01, rmode_10, rmode_11 : std_logic ;
    signal max_num, inf_out : std_logic ;
    signal max_num_t1, max_num_t2, max_num_t3,max_num_t4,inf_out_t1 : std_logic ;
    signal underflow_fmul : std_logic ;
    signal overflow_fdiv : std_logic ;
    signal undeflow_div : std_logic ;
    signal f2i_ine : std_logic ;
    signal fracta_del, fractb_del : std_logic_vector (26 downto 0);
    signal grs_del : std_logic_vector (2 downto 0);
    signal dn_del : std_logic ;
    signal exp_in_del : std_logic_vector (7 downto 0);
    signal exp_out_del : std_logic_vector (7 downto 0);
    signal fract_out_del : std_logic_vector (22 downto 0);
    signal fract_in_del : std_logic_vector (47 downto 0);
    signal overflow_del : std_logic ;
    signal exp_ovf_del : std_logic_vector (1 downto 0);
    signal fract_out_x_del, fract_out_rnd2a_del : std_logic_vector (22 downto 0);
    signal trunc_xx_del : std_logic_vector (24 downto 0);
    signal exp_rnd_adj2a_del : std_logic ;
    signal fract_dn_del : std_logic_vector (22 downto 0);
    signal div_opa_ldz_del : std_logic_vector (4 downto 0);
    signal fracta_div_del : std_logic_vector (23 downto 0);
    signal fractb_div_del : std_logic_vector (23 downto 0);
    signal div_inf_del : std_logic ;
    signal fi_ldz_2_del : std_logic_vector (7 downto 0);
    signal inf_out_del, max_out_del : std_logic ;
    signal fi_ldz_del : std_logic_vector (5 downto 0);
    signal rx_del : std_logic ;
    signal ez_del : std_logic ;
    signal lr : std_logic ;
    signal exp_div_del : std_logic_vector (7 downto 0);
    signal z : std_logic;
    signal undeflow_div_p1 : std_logic ;
    signal undeflow_div_p2 : std_logic ;
    signal undeflow_div_p3 : std_logic ;
    signal undeflow_div_p4 : std_logic ;
    signal undeflow_div_p5 : std_logic ;
    signal undeflow_div_p6 : std_logic ;
    signal undeflow_div_p7 : std_logic ;
    signal undeflow_div_p8 : std_logic ;
    signal undeflow_div_p9 : std_logic ;
    signal undeflow_div_p10 : std_logic ;

    CONSTANT f2i_emax : std_logic_vector(7 DOWNTO 0) := X"9d";
    
BEGIN

    op_dn <= opa_dn or opb_dn ;
    op_mul <= '1'WHEN (fpu_op(2 DOWNTO 0)="010") ELSE '0';
    op_div <= '1'WHEN (fpu_op(2 DOWNTO 0)="011") ELSE '0';
    op_i2f <= '1'WHEN (fpu_op(2 DOWNTO 0)="100") ELSE '0';
    op_f2i <= '1'WHEN (fpu_op(2 DOWNTO 0)="101") ELSE '0';

    ---------------------------------------------------------------------------
    -- Normalize and Round Logic
    ---------------------------------------------------------------------------
    
    -- Count Leading zeros in fraction
    PROCESS (fract_in)
    BEGIN 
        IF fract_in(47) =  '1' THEN fi_ldz <=  conv_std_logic_vector(1,6);
        ELSIF fract_in(47 DOWNTO 46) = "01" THEN fi_ldz <=  conv_std_logic_vector(2,6);
        ELSIF fract_in(47 DOWNTO 45) = "001" THEN fi_ldz <=  conv_std_logic_vector(3,6);
        ELSIF fract_in(47 DOWNTO 44) = "0001" THEN fi_ldz <=  conv_std_logic_vector(4,6);
        ELSIF fract_in(47 DOWNTO 43) = "00001" THEN fi_ldz <=  conv_std_logic_vector(5,6);
        ELSIF fract_in(47 DOWNTO 42) = "000001" THEN fi_ldz <=  conv_std_logic_vector(6,6);
        ELSIF fract_in(47 DOWNTO 41) = "0000001" THEN fi_ldz <=  conv_std_logic_vector(7,6);
        ELSIF fract_in(47 DOWNTO 40) = "00000001" THEN fi_ldz <=  conv_std_logic_vector(8,6);
        ELSIF fract_in(47 DOWNTO 39) = "000000001" THEN fi_ldz <=  conv_std_logic_vector(9,6);
        ELSIF fract_in(47 DOWNTO 38) = "0000000001" THEN fi_ldz <=  conv_std_logic_vector(10,6);
        ELSIF fract_in(47 DOWNTO 37) = "00000000001" THEN fi_ldz <=  conv_std_logic_vector(11,6);
        ELSIF fract_in(47 DOWNTO 36) = "000000000001" THEN fi_ldz <=  conv_std_logic_vector(12,6);
        ELSIF fract_in(47 DOWNTO 35) = "0000000000001" THEN fi_ldz <=  conv_std_logic_vector(13,6);
        ELSIF fract_in(47 DOWNTO 34) = "00000000000001" THEN fi_ldz <=  conv_std_logic_vector(14,6);
        ELSIF fract_in(47 DOWNTO 33) = "000000000000001" THEN fi_ldz <=  conv_std_logic_vector(15,6);
        ELSIF fract_in(47 DOWNTO 32) = "0000000000000001" THEN fi_ldz <=  conv_std_logic_vector(16,6);
        ELSIF fract_in(47 DOWNTO 31) = "00000000000000001" THEN fi_ldz <=  conv_std_logic_vector(17,6);
        ELSIF fract_in(47 DOWNTO 30) = "000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(18,6);
        ELSIF fract_in(47 DOWNTO 29) = "0000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(19,6);
        ELSIF fract_in(47 DOWNTO 28) = "00000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(20,6);
        ELSIF fract_in(47 DOWNTO 27) = "000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(21,6);
        ELSIF fract_in(47 DOWNTO 26) = "0000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(22,6);
        ELSIF fract_in(47 DOWNTO 25) = "00000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(23,6);
        ELSIF fract_in(47 DOWNTO 24) = "000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(24,6);
        ELSIF fract_in(47 DOWNTO 23) = "0000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(25,6);
        ELSIF fract_in(47 DOWNTO 22) = "00000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(26,6);
        ELSIF fract_in(47 DOWNTO 21) = "000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(27,6);
        ELSIF fract_in(47 DOWNTO 20) = "0000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(28,6);
        ELSIF fract_in(47 DOWNTO 19) = "00000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(29,6);
        ELSIF fract_in(47 DOWNTO 18) = "000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(30,6);
        ELSIF fract_in(47 DOWNTO 17) = "0000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(31,6);
        ELSIF fract_in(47 DOWNTO 16) = "00000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(32,6);
        ELSIF fract_in(47 DOWNTO 15) = "000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(33,6);
        ELSIF fract_in(47 DOWNTO 14) = "0000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(34,6);
        ELSIF fract_in(47 DOWNTO 13) = "00000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(35,6);
        ELSIF fract_in(47 DOWNTO 12) = "000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(36,6);
        ELSIF fract_in(47 DOWNTO 11) = "0000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(37,6);
        ELSIF fract_in(47 DOWNTO 10) = "00000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(38,6);
        ELSIF fract_in(47 DOWNTO 9) = "000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(39,6);
        ELSIF fract_in(47 DOWNTO 8) = "0000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(40,6);
        ELSIF fract_in(47 DOWNTO 7) = "00000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(41,6);
        ELSIF fract_in(47 DOWNTO 6) = "000000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(42,6);
        ELSIF fract_in(47 DOWNTO 5) = "0000000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(43,6);
        ELSIF fract_in(47 DOWNTO 4) = "00000000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(44,6);
        ELSIF fract_in(47 DOWNTO 3) = "000000000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(45,6);
        ELSIF fract_in(47 DOWNTO 2) = "0000000000000000000000000000000000000000000001" THEN fi_ldz <=  conv_std_logic_vector(46,6);
        ELSIF fract_in(47 DOWNTO 1) = "00000000000000000000000000000000000000000000001"  THEN fi_ldz <=  conv_std_logic_vector(47,6);
        ELSIF fract_in(47 DOWNTO 1) = "00000000000000000000000000000000000000000000000" THEN fi_ldz <=  conv_std_logic_vector(48,6);
        ELSE fi_ldz <= (OTHERS => 'X');
        END IF;
    END PROCESS;

    -- Normalize
    exp_in_ff <= and_reduce(exp_in);
    exp_in_00 <= NOT (or_reduce(exp_in));
    exp_in_80 <= exp_in(7) AND NOT (or_reduce(exp_in(6 DOWNTO 0)));
    exp_out_ff <= and_reduce(exp_out);
    exp_out_00 <= NOT (or_reduce(exp_out));
    exp_out_fe <= (and_reduce(exp_out(7 DOWNTO 1))) AND NOT exp_out(0);
    exp_out_final_ff <= and_reduce(exp_out_final);

    fract_out_7fffff <= and_reduce(fract_out);
    fract_out_00 <= NOT (or_reduce(fract_out));
    fract_in_00 <= NOT (or_reduce(fract_in));

    rmode_00 <= '1' WHEN (rmode = "00") ELSE '0';
    rmode_01 <= '1' WHEN (rmode = "01") ELSE '0';
    rmode_10 <= '1' WHEN (rmode = "10") ELSE '0';
    rmode_11 <= '1' WHEN (rmode = "11") ELSE '0';