receive_tb.v.svn-base

一个用verilog实现的fpga上的uart接口模块

`timescale 1ns/1ns
module receive_tb;
    
    reg clk16x,rec_in;
    reg rst;
    wire [7:0] data_out ;
    wire data_ready ;
    wire format_error ;
    wire parity_error ;
    initial
    begin
        clk16x<= 0;
        rec_in<=1;
        rst <= 0;
        #32 rst <=1;
        #32 rst <=0;
	#64 rec_in<=1;
	#32 rec_in<=0;
	#32 rec_in<=1;
	#64 rec_in<=0;
	#32 rec_in<=1;
	#32 rec_in<=0;
	#32 rec_in<=1;
	#65 rec_in<=0;
	#32 rec_in<=1;
	#32 rec_in<=0;
	#64 rec_in<=1;
	#32 rec_in<=0;
	#64 rec_in<=1;
	#64 rec_in<=0;
	#96 rec_in<=1;
	#32 rec_in<=0;
	#96 rec_in<=1;
	#64 rec_in<=0;
	#32 rec_in<=1;
	#96 rec_in<=0;
	#32 rec_in<=1;
	#64 rec_in<=0;
	#96 rec_in<=1;
	#32 rec_in<=0;
	#96 rec_in<=1;
	#32 rec_in<=0;
	#32 rec_in<=1;
	#32 rec_in<=0;
	#64 rec_in<=1;
        #1000 $stop;
    end
    always #1 clk16x = ~clk16x;
    receive m(rec_in,data_out,data_ready,format_error,parity_error,clk16x,rst) ;
endmodule