uart_test_9600.v.svn-base

一个用verilog实现的fpga上的uart接口模块

module uart_test_9600(clk, //clock 125MHZ
rst,	//reset
din,	//8 bits input
s_in,	//serial input
s_out,//serial output
wr_en,//write enable
interrupt,   //data ready
data_out
);

input clk,rst;
input [7:0]din;
input wr_en,s_in;
output s_out;
output interrupt;
output [7:0]data_out;

reg clk_9600;
reg clk_153600;
reg[7:0] data_in;
reg[7:0] data_out;
wire[7:0] dout;
parameter port=8'haa;
reg [13:0]clk_9600_counter;
reg [9:0]clk_153600_counter;
reg flag_9600,flag_153600;//posedge


uart  uu(.s_out(s_out),.data_in(din),.wr(wr_en),.clk1x(clk_9600),.rst(rst),.port(port),.s_in(s_in),.interrupt(interrupt),.data_out(dout),.clk16x(clk_153600));
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		data_in<=8'b11111111;//initial serial output is always 1 
	end
	else if(wr_en)//write enable
		data_in<=din;
	
end
always @(posedge interrupt or posedge rst)
begin
	if(rst)
	begin
		data_out<=8'b11111111;
	end
	else if(interrupt)
		data_out<=dout;
	
end

//9600HZ clock generation
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		clk_9600_counter<=0;
		flag_9600<=0;
		clk_9600<=1;
	end
	else if(clk_9600_counter==13020)//13020
	begin 
		flag_9600<=1;
		clk_9600<=0;
		clk_9600_counter<=0;
	end
	else if(clk_9600_counter==1&&flag_9600==1)
	begin
		flag_9600<=0;
		clk_9600<=1;
		clk_9600_counter<=0;
	end
	else
	begin
		clk_9600_counter<=clk_9600_counter+1;
	end
end

//153600HZ clock generation
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		clk_153600_counter<=0;
		flag_153600<=0;
		clk_153600<=1;
	end
	else if(clk_153600_counter==814)//814
	begin 
		flag_153600<=1;
		clk_153600<=0;
		clk_153600_counter<=0;
	end
	else if(clk_153600_counter==1&&flag_153600==1)
	begin
		flag_153600<=0;
		clk_153600<=1;
		clk_153600_counter<=0;
	end
	else
	begin
		clk_153600_counter<=clk_153600_counter+1;
	end
end


endmodule