uart.v.svn-base

一个用verilog实现的fpga上的uart接口模块

`include "receive.v"
`include "transmit.v"

module uart(
s_in,  //serial input
s_out, //serial output
data_in,  //data to be transmit
data_out,  //data of recieving
wr,    //write enable
clk1x,  //1 time clock
clk16x, //16 times clock
rst,   //reset
port,   //port number
interrupt  //interrupt signal
);
input  clk1x,clk16x,rst,s_in,wr;
input [7:0] data_in;
input [7:0] port;
output [7:0] data_out;
output s_out;
output interrupt;


reg illegal_write;//not implement
reg [7:0] int_state;


//call the recieve and transmit module 
receive rec(s_in,data_out,data_ready,format_error,parity_error,clk16x,rst) ;
transmit tra(.clk(clk1x),.rst(rst),.data_in(data_in),.write(wr),.serial_out(s_out),.tx_complete(tx_complete),.port(port));
always @(posedge clk1x or posedge rst)
begin
	if(rst)
		illegal_write<=0;
	else if(wr&&!tx_complete)
		illegal_write<=1;
	else 
		illegal_write<=0;
end
/*
always  @(posedge parity_error or posedge format_error or posedge data_ready or posedge illegal_write or posedge rst)
begin
	if(rst)
	begin
		int_state<=0;
		illegal_write<=0;
	end
	else
	begin
		int_state[0]<=parity_error;
		int_state[1]<=format_error;
		int_state[2]<=data_ready;
		int_state[3]<=illegal_write;
		int_state[4]<=0;
		int_state[5]<=0;
		int_state[6]<=0;
		int_state[7]<=0;
	end
end
*/

//interrupt information reg
always  @(parity_error or format_error or data_ready or illegal_write )
begin
		int_state[0]<=parity_error;
		int_state[1]<=format_error;
		int_state[2]<=data_ready;
		int_state[3]<=illegal_write;
		int_state[4]<=0;
		int_state[5]<=0;
		int_state[6]<=0;
		int_state[7]<=0;
end

// generate interrupt signal;
assign interrupt=parity_error|format_error|data_ready|illegal_write;

endmodule