transmit.v.svn-base

一个用verilog实现的fpga上的uart接口模块

module transmit(clk,		//clock
rst,		//reset
data_in,	//data input
write,	//write enable
serial_out,	//serial output
tx_complete,	//transmit complete
port
);
input clk,rst,write;
output serial_out,tx_complete;
input [7:0] data_in;
input [7:0] port;

reg serial_out;  
reg [7:0] tx_data;  //the reg to store the data sended
reg parity; //the parity bit
reg pre_wr;//the write signal at last posedge of clock
reg cur_wr;//the write signal at current posedge of clock
reg begin_tx;  //the flag of beginning sending data
reg tx_complete;  //the state of tranmit   1 means trnas complete while 0 means not complete
reg [3:0]num_tx;

parameter port_id =8'haa;

always @(posedge clk or posedge rst)
begin
	if(rst)   //if reset
	begin
		serial_out<=1;	//always output 1
		parity<=1;		//odd verify
		begin_tx<=0;	//the flag of beginning sending data
		tx_data<=0;		//the data be sended
	end
	else if(port==port_id)
	begin
		if(!pre_wr&&cur_wr)//capture the posedge of write enable
		begin
			begin_tx<=1;			//set the  flag of beginning sending data is true
			tx_data<=data_in;  //load the data form the bus
		end
		else if(num_tx==4'b0001)
		begin
			serial_out<=0;			//send begin bit
		end
		else if(num_tx>=4'b0010&&num_tx<=4'b1001)
		begin
			tx_data[6:0] <= tx_data[7:1] ;
			tx_data[7] <= 1'b0 ;
			serial_out <= tx_data[0] ;
			parity <= parity ^ tx_data[0] ;  //generate parity verify bit
		end
		else if(num_tx==4'b1010)
		begin
			serial_out<=parity;			//send the parity verify bit
		end
		else if(num_tx==4'b1011)
		begin
			serial_out<=1;				//send end bit
		end
		else if(num_tx==4'b1100)
		begin
			serial_out<=1;			//send end bit
		end
		else if(num_tx==4'b1101)		//initial 
		begin
			serial_out<=1;
			parity<=1;
			begin_tx<=0;
		end
	end
end

//set the precious and current write enable signal to capture the posedge of write enable
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		pre_wr<=0; 
		cur_wr<=0;
	end
	else 
	begin
		pre_wr<=cur_wr;
		cur_wr<=write;
	end
end

//set the counter of sending data
always @(posedge clk or posedge rst)
begin
	if(rst)
	begin
		num_tx<=0;
		tx_complete<=1;
	end
	else if(!begin_tx)// if not begin always transmit complete statement
	begin
		num_tx<=0;
		tx_complete<=1;  
	end
	else // counter
	begin
		num_tx<=num_tx+1;
		tx_complete<=0;
	end
end
endmodule