state1.srs

人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习

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# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Dec 16 15:01:09 2005
#
#
#OPTIONS:"|-fixsmult|-I|C:\\prj\\FSM_abc\\state1\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\ec.v|-autosm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\ec.v":1110443424
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\lucent\\ec.v":1110443424
#CUR:"C:\\prj\\FSM_abc\\state1\\state1.v":1134716328
#CUR:"C:\\prj\\FSM_abc\\state1\\state1.v":1134716328
f "C:\eda\synplicity\fpga_81\lib\lucent\ec.v"; # file 0
af .is_verilog 1;
f "C:\prj\FSM_abc\state1\state1.v"; # file 1
af .is_verilog 1;
@E
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R4@@::cn.c4:n.:dR8NMP4RF_#._JGlkN4RF_#._JGlkN1RhrR49k_M4H
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