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📄 state2_rm.tcl

📁 人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习
💻 TCL
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set_global_assignment -name ROOT "|state2" -remove 
set_global_assignment -name FAMILY -remove 
set_global_assignment -section_id clk_setting -name DUTY_CYCLE "50.00" -remove 
set_instance_assignment -entity state2 -to clk -name GLOBAL_SIGNAL ON -remove 
set_instance_assignment -entity state2 -to clk -name USE_CLOCK_SETTINGS clk_setting -remove 
set_global_assignment -section_id clk_setting -name FMAX_REQUIREMENT "1000.0MHZ" -remove 
set_global_assignment -name TAO_FILE "myresults.tao" -remove
set_global_assignment -name SOURCES_PER_DESTINATION_INCLUDE_COUNT "1000" -remove 
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON -remove 
set_global_assignment -name REMOVE_DUPLICATE_LOGIC "OFF" -remove 
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS "OFF" -remove 
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS "ON" -remove 
set_global_assignment -name EDA_RESYNTHESIS_TOOL "AMPLIFY" -remove

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