firfilter_da.tan.qmsg

分布式算法在实现乘加功能时

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register count_4b\[2\] register DIN_8b_3\[5\] 321.03 MHz 3.115 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 321.03 MHz between source register \"count_4b\[2\]\" and destination register \"DIN_8b_3\[5\]\" (period= 3.115 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.935 ns + Longest register register " "Info: + Longest register to register delay is 2.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_4b\[2\] 1 REG LCFF_X25_Y9_N21 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y9_N21; Fanout = 16; REG Node = 'count_4b\[2\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { count_4b[2] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.228 ns) 1.441 ns DIN_8b_3\[1\]~130 2 COMB LCCOMB_X25_Y9_N30 8 " "Info: 2: + IC(1.213 ns) + CELL(0.228 ns) = 1.441 ns; Loc. = LCCOMB_X25_Y9_N30; Fanout = 8; COMB Node = 'DIN_8b_3\[1\]~130'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.441 ns" { count_4b[2] DIN_8b_3[1]~130 } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.748 ns) + CELL(0.746 ns) 2.935 ns DIN_8b_3\[5\] 3 REG LCFF_X25_Y10_N31 10 " "Info: 3: + IC(0.748 ns) + CELL(0.746 ns) = 2.935 ns; Loc. = LCFF_X25_Y10_N31; Fanout = 10; REG Node = 'DIN_8b_3\[5\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { DIN_8b_3[1]~130 DIN_8b_3[5] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.974 ns ( 33.19 % ) " "Info: Total cell delay = 0.974 ns ( 33.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.961 ns ( 66.81 % ) " "Info: Total interconnect delay = 1.961 ns ( 66.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { count_4b[2] DIN_8b_3[1]~130 DIN_8b_3[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { count_4b[2] DIN_8b_3[1]~130 DIN_8b_3[5] } { 0.000ns 1.213ns 0.748ns } { 0.000ns 0.228ns 0.746ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.485 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1007 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1007; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.485 ns DIN_8b_3\[5\] 3 REG LCFF_X25_Y10_N31 10 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X25_Y10_N31; Fanout = 10; REG Node = 'DIN_8b_3\[5\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { CLK~clkctrl DIN_8b_3[5] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.24 % ) " "Info: Total cell delay = 1.472 ns ( 59.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.76 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl DIN_8b_3[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_3[5] } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.481 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1007 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1007; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 2.481 ns count_4b\[2\] 3 REG LCFF_X25_Y9_N21 16 " "Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X25_Y9_N21; Fanout = 16; REG Node = 'count_4b\[2\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { CLK~clkctrl count_4b[2] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.33 % ) " "Info: Total cell delay = 1.472 ns ( 59.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 40.67 % ) " "Info: Total interconnect delay = 1.009 ns ( 40.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { CLK CLK~clkctrl count_4b[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { CLK CLK~combout CLK~clkctrl count_4b[2] } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl DIN_8b_3[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_3[5] } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { CLK CLK~clkctrl count_4b[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { CLK CLK~combout CLK~clkctrl count_4b[2] } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { count_4b[2] DIN_8b_3[1]~130 DIN_8b_3[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { count_4b[2] DIN_8b_3[1]~130 DIN_8b_3[5] } { 0.000ns 1.213ns 0.748ns } { 0.000ns 0.228ns 0.746ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl DIN_8b_3[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_3[5] } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { CLK CLK~clkctrl count_4b[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { CLK CLK~combout CLK~clkctrl count_4b[2] } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DIN_8b_4\[4\] DIN\[4\] CLK 4.372 ns register " "Info: tsu for register \"DIN_8b_4\[4\]\" (data pin = \"DIN\[4\]\", clock pin = \"CLK\") is 4.372 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.772 ns + Longest pin register " "Info: + Longest pin to register delay is 6.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns DIN\[4\] 1 PIN PIN_T1 14 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_T1; Fanout = 14; PIN Node = 'DIN\[4\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN[4] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.633 ns) + CELL(0.309 ns) 6.772 ns DIN_8b_4\[4\] 2 REG LCFF_X26_Y13_N13 15 " "Info: 2: + IC(5.633 ns) + CELL(0.309 ns) = 6.772 ns; Loc. = LCFF_X26_Y13_N13; Fanout = 15; REG Node = 'DIN_8b_4\[4\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.942 ns" { DIN[4] DIN_8b_4[4] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.139 ns ( 16.82 % ) " "Info: Total cell delay = 1.139 ns ( 16.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.633 ns ( 83.18 % ) " "Info: Total interconnect delay = 5.633 ns ( 83.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.772 ns" { DIN[4] DIN_8b_4[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "6.772 ns" { DIN[4] DIN[4]~combout DIN_8b_4[4] } { 0.000ns 0.000ns 5.633ns } { 0.000ns 0.830ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.490 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1007 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1007; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns DIN_8b_4\[4\] 3 REG LCFF_X26_Y13_N13 15 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X26_Y13_N13; Fanout = 15; REG Node = 'DIN_8b_4\[4\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { CLK~clkctrl DIN_8b_4[4] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { CLK CLK~clkctrl DIN_8b_4[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_4[4] } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.772 ns" { DIN[4] DIN_8b_4[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "6.772 ns" { DIN[4] DIN[4]~combout DIN_8b_4[4] } { 0.000ns 0.000ns 5.633ns } { 0.000ns 0.830ns 0.309ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { CLK CLK~clkctrl DIN_8b_4[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_4[4] } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Dout\[2\] temp_3\[12\] 6.078 ns register " "Info: tco from clock \"CLK\" to destination pin \"Dout\[2\]\" through register \"temp_3\[12\]\" is 6.078 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.482 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1007 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1007; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.618 ns) 2.482 ns temp_3\[12\] 3 REG LCFF_X26_Y9_N1 1 " "Info: 3: + IC(0.667 ns) + CELL(0.618 ns) = 2.482 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'temp_3\[12\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { CLK~clkctrl temp_3[12] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.31 % ) " "Info: Total cell delay = 1.472 ns ( 59.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 40.69 % ) " "Info: Total interconnect delay = 1.010 ns ( 40.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { CLK CLK~clkctrl temp_3[12] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { CLK CLK~combout CLK~clkctrl temp_3[12] } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 321 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.502 ns + Longest register pin " "Info: + Longest register to pin delay is 3.502 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp_3\[12\] 1 REG LCFF_X26_Y9_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'temp_3\[12\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp_3[12] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.348 ns) + CELL(2.154 ns) 3.502 ns Dout\[2\] 2 PIN PIN_R1 0 " "Info: 2: + IC(1.348 ns) + CELL(2.154 ns) = 3.502 ns; Loc. = PIN_R1; Fanout = 0; PIN Node = 'Dout\[2\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.502 ns" { temp_3[12] Dout[2] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.154 ns ( 61.51 % ) " "Info: Total cell delay = 2.154 ns ( 61.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.348 ns ( 38.49 % ) " "Info: Total interconnect delay = 1.348 ns ( 38.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.502 ns" { temp_3[12] Dout[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "3.502 ns" { temp_3[12] Dout[2] } { 0.000ns 1.348ns } { 0.000ns 2.154ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { CLK CLK~clkctrl temp_3[12] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { CLK CLK~combout CLK~clkctrl temp_3[12] } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.502 ns" { temp_3[12] Dout[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "3.502 ns" { temp_3[12] Dout[2] } { 0.000ns 1.348ns } { 0.000ns 2.154ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "DIN_8b_14\[6\] DIN\[6\] CLK -2.286 ns register " "Info: th for register \"DIN_8b_14\[6\]\" (data pin = \"DIN\[6\]\", clock pin = \"CLK\") is -2.286 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.479 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.479 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1007 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1007; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.618 ns) 2.479 ns DIN_8b_14\[6\] 3 REG LCFF_X26_Y6_N27 10 " "Info: 3: + IC(0.664 ns) + CELL(0.618 ns) = 2.479 ns; Loc. = LCFF_X26_Y6_N27; Fanout = 10; REG Node = 'DIN_8b_14\[6\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.282 ns" { CLK~clkctrl DIN_8b_14[6] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.38 % ) " "Info: Total cell delay = 1.472 ns ( 59.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 40.62 % ) " "Info: Total interconnect delay = 1.007 ns ( 40.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { CLK CLK~clkctrl DIN_8b_14[6] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_14[6] } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.914 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 0.800 ns DIN\[6\] 1 PIN PIN_R6 14 " "Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_R6; Fanout = 14; PIN Node = 'DIN\[6\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN[6] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.906 ns) + CELL(0.053 ns) 4.759 ns DIN_8b_14\[6\]~feeder 2 COMB LCCOMB_X26_Y6_N26 1 " "Info: 2: + IC(3.906 ns) + CELL(0.053 ns) = 4.759 ns; Loc. = LCCOMB_X26_Y6_N26; Fanout = 1; COMB Node = 'DIN_8b_14\[6\]~feeder'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.959 ns" { DIN[6] DIN_8b_14[6]~feeder } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.914 ns DIN_8b_14\[6\] 3 REG LCFF_X26_Y6_N27 10 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.914 ns; Loc. = LCFF_X26_Y6_N27; Fanout = 10; REG Node = 'DIN_8b_14\[6\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { DIN_8b_14[6]~feeder DIN_8b_14[6] } "NODE_NAME" } } { "firfilter_da.v" "" { Text "E:/firfilter_da/firfilter_da.v" 162 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.008 ns ( 20.51 % ) " "Info: Total cell delay = 1.008 ns ( 20.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.906 ns ( 79.49 % ) " "Info: Total interconnect delay = 3.906 ns ( 79.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.914 ns" { DIN[6] DIN_8b_14[6]~feeder DIN_8b_14[6] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "4.914 ns" { DIN[6] DIN[6]~combout DIN_8b_14[6]~feeder DIN_8b_14[6] } { 0.000ns 0.000ns 3.906ns 0.000ns } { 0.000ns 0.800ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.479 ns" { CLK CLK~clkctrl DIN_8b_14[6] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.479 ns" { CLK CLK~combout CLK~clkctrl DIN_8b_14[6] } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.914 ns" { DIN[6] DIN_8b_14[6]~feeder DIN_8b_14[6] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "4.914 ns" { DIN[6] DIN[6]~combout DIN_8b_14[6]~feeder DIN_8b_14[6] } { 0.000ns 0.000ns 3.906ns 0.000ns } { 0.000ns 0.800ns 0.053ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}