_primary.vhd

来自「分布式算法在实现乘加功能时」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity firfilter_da is
    port(
        CLK             : in     vl_logic;
        Reset           : in     vl_logic;
        DIN             : in     vl_logic_vector(7 downto 0);
        Dout            : out    vl_logic_vector(15 downto 0)
    );
end firfilter_da;