firfilter_da.map.summary

来自「分布式算法在实现乘加功能时」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Mon Nov 26 20:36:32 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : firfilter_da
Top-level Entity Name : firfilter_da
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 915
    Dedicated logic registers : 1,007
Total registers : 1007
Total pins : 26
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0