📄 firfilter_da.v.bak
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//////////////////////////////////////////////////////////////////
// //
// Copyright(c) : 2007,EDA,PHY,WHU //
// //
//--------------------------------------------------------------//
// FILE NAME : firfilter_da.v //
// TYPE : module //
// AUTHOR : Eric.Hui.Shao //
// EMAIL@ : Tandywhu@163.com //
//--------------------------------------------------------------//
// Purpose : FIR da filter //
// Assumptions : none //
// Limitations : none //
// Known Errors : none //
// Notes : (16 steps) //
// : //
//--------------------------------------------------------------//
// Release history //
// 1.0 25th November 2007 initial version //
// //
//////////////////////////////////////////////////////////////////
//-----------------------
// module description
//-----------------------
module firfilter_da( CLK,
Reset,
DIN,
Dout
);
//-----------------------
// port declaration
//-----------------------
input CLK;
input Reset;
input [7:0] DIN;
output [15:0] Dout;
//输入信号寄存器
reg [7:0] DIN_8b_0;
reg [7:0] DIN_8b_1;
reg [7:0] DIN_8b_2;
reg [7:0] DIN_8b_3;
reg [7:0] DIN_8b_4;
reg [7:0] DIN_8b_5;
reg [7:0] DIN_8b_6;
reg [7:0] DIN_8b_7;
reg [7:0] DIN_8b_8;
reg [7:0] DIN_8b_9;
reg [7:0] DIN_8b_10;
reg [7:0] DIN_8b_11;
reg [7:0] DIN_8b_12;
reg [7:0] DIN_8b_13;
reg [7:0] DIN_8b_14;
reg [25:0] temp_1_1,temp_1_2,temp_1_3,temp_1_4;
reg [25:0] temp_2_1,temp_2_2;
reg [25:0] temp_3;
assign Dout = temp_3[25:10];
function[15:0] look_A3_A0;
input [3:0] DIN;
begin
case(DIN)
4'b0000: look_A3_A0=16'h0;
4'b0001: look_A3_A0=16'h0;
4'b0010: look_A3_A0=16'h65;
4'b0011: look_A3_A0=16'h65;
4'b0100: look_A3_A0=16'h18f;
4'b0101: look_A3_A0=16'h18f;
4'b0110: look_A3_A0=16'h1f4;
4'b0111: look_A3_A0=16'h1f4;
4'b1000: look_A3_A0=16'h35a;
4'b1001: look_A3_A0=16'h35a;
4'b1010: look_A3_A0=16'h3bf;
4'b1011: look_A3_A0=16'h3bf;
4'b1100: look_A3_A0=16'h4e9;
4'b1101: look_A3_A0=16'h4e9;
4'b1110: look_A3_A0=16'h54e;
4'b1111: look_A3_A0=16'h54e;
endcase
end
endfunction
function[15:0] look_A7_A4;
input [3:0] DIN;
begin
case(DIN)
4'b0000: look_A7_A4=16'h0;
4'b0001: look_A7_A4=16'h579;
4'b0010: look_A7_A4=16'h78e;
4'b0011: look_A7_A4=16'hd07;
4'b0100: look_A7_A4=16'h935;
4'b0101: look_A7_A4=16'heae;
4'b0110: look_A7_A4=16'h10c3;
4'b0111: look_A7_A4=16'h163c;
4'b1000: look_A7_A4=16'h0a1f;
4'b1001: look_A7_A4=16'h0f98;
4'b1010: look_A7_A4=16'h11ad;
4'b1011: look_A7_A4=16'h1726;
4'b1100: look_A7_A4=16'h1354;
4'b1101: look_A7_A4=16'h18cd;
4'b1110: look_A7_A4=16'h1ae2;
4'b1111: look_A7_A4=16'h205b;
endcase
end
endfunction
reg [16:0] lookup0_1,lookup0_2,lookup0_3,lookup0_4,
lookup1_1,lookup1_2,lookup1_3,lookup1_4,
lookup2_1,lookup2_2,lookup2_3,lookup2_4,
lookup3_1,lookup3_2,lookup3_3,lookup3_4,
lookup4_1,lookup4_2,lookup4_3,lookup4_4,
lookup5_1,lookup5_2,lookup5_3,lookup5_4,
lookup6_1,lookup6_2,lookup6_3,lookup6_4,
lookup7_1,lookup7_2,lookup7_3,lookup7_4;
reg [17:0] sum0_1,sum0_2,sum1_1,sum1_2,
sum2_1,sum2_2,sum3_1,sum3_2,
sum4_1,sum4_2,sum5_1,sum5_2,
sum6_1,sum6_2,sum7_1,sum7_2;
reg [18:0] sum0,sum1,sum2,sum3,sum4,sum5,sum6,sum7;
reg [3:0] count_4b;
// 输入信号的初始化
always @(posedge CLK or posedge Reset)
begin
if(Reset)
begin
count_4b<=0;
DIN_8b_0<=0;
DIN_8b_1<=0;
DIN_8b_2<=0;
DIN_8b_3<=0;
DIN_8b_4<=0;
DIN_8b_5<=0;
DIN_8b_6<=0;
DIN_8b_7<=0;
DIN_8b_8<=0;
DIN_8b_9<=0;
DIN_8b_10<=0;
DIN_8b_11<=0;
DIN_8b_12<=0;
DIN_8b_13<=0;
DIN_8b_14<=0;
end
else
begin
if(count_4b==15)
begin
DIN_8b_0<=DIN_8b_1;
DIN_8b_1<=DIN_8b_2;
DIN_8b_2<=DIN_8b_3;
DIN_8b_3<=DIN_8b_4;
DIN_8b_4<=DIN_8b_5;
DIN_8b_5<=DIN_8b_6;
DIN_8b_6<=DIN_8b_7;
DIN_8b_7<=DIN_8b_8;
DIN_8b_8<=DIN_8b_9;
DIN_8b_9<=DIN_8b_10;
DIN_8b_10<=DIN_8b_11;
DIN_8b_11<=DIN_8b_12;
DIN_8b_12<=DIN_8b_13;
DIN_8b_13<=DIN_8b_14;
DIN_8b_14<=DIN;
end
else
begin
case(count_4b)
'd0: DIN_8b_0=DIN;
'd1: DIN_8b_1=DIN;
'd2: DIN_8b_2=DIN;
'd3: DIN_8b_3=DIN;
'd4: DIN_8b_4=DIN;
'd5: DIN_8b_5=DIN;
'd6: DIN_8b_6=DIN;
'd7: DIN_8b_7=DIN;
'd8: DIN_8b_8=DIN;
'd9: DIN_8b_9=DIN;
'd10: DIN_8b_10=DIN;
'd11: DIN_8b_11=DIN;
'd12: DIN_8b_12=DIN;
'd13: DIN_8b_13=DIN;
'd14: DIN_8b_14=DIN;
default:;
endcase
count_4b=count_4b+1;
end
end
end
always @(posedge CLK or posedge Reset)
begin
if(Reset)
begin
//0
lookup0_1 <= 0;
lookup0_2 <= 0;
lookup0_3 <= 0;
lookup0_4 <= 0;
sum0_1 <= 0;
sum0_2 <= 0;
sum0 <= 0;
//1
lookup1_1 <= 0;
lookup1_2 <= 0;
lookup1_3 <= 0;
lookup1_4 <= 0;
sum1_1 <= 0;
sum1_2 <= 0;
sum1 <= 0;
//2
lookup2_1 <= 0;
lookup2_2 <= 0;
lookup2_3 <= 0;
lookup2_4 <= 0;
sum2_1 <= 0;
sum2_2 <= 0;
sum2 <= 0;
//3
lookup3_1 <= 0;
lookup3_2 <= 0;
lookup3_3 <= 0;
lookup3_4 <= 0;
sum3_1 <= 0;
sum3_2 <= 0;
sum3 <= 0;
//4
lookup4_1 <= 0;
lookup4_2 <= 0;
lookup4_3 <= 0;
lookup4_4 <= 0;
sum4_1 <= 0;
sum4_2 <= 0;
sum4 <= 0;
//5
lookup5_1 <= 0;
lookup5_2 <= 0;
lookup5_3 <= 0;
lookup5_4 <= 0;
sum5_1 <= 0;
sum5_2 <= 0;
sum5 <= 0;
//6
lookup6_1 <= 0;
lookup6_2 <= 0;
lookup6_3 <= 0;
lookup6_4 <= 0;
sum6_1 <= 0;
sum6_2 <= 0;
sum6 <= 0;
//7
lookup7_1 <= 0;
lookup7_2 <= 0;
lookup7_3 <= 0;
lookup7_4 <= 0;
sum7_1 <= 0;
sum7_2 <= 0;
sum7 <= 0;
end
else
if(count_4b==15)
begin
//0
lookup0_1 <= look_A3_A0({DIN_8b_12[0],DIN_8b_13[0],DIN_8b_14[0],DIN[0]});
lookup0_2 <= look_A7_A4({DIN_8b_8[0],DIN_8b_9[0],DIN_8b_10[0],DIN_8b_11[0]});
lookup0_3 <= look_A7_A4({DIN_8b_7[0],DIN_8b_6[0],DIN_8b_5[0],DIN_8b_4[0]});
lookup0_4 <= look_A3_A0({DIN_8b_3[0],DIN_8b_2[0],DIN_8b_1[0],DIN_8b_0[0]});
sum0_1 <= lookup0_1 + lookup0_2;
sum0_2 <= lookup0_3 + lookup0_4;
sum0 <= sum0_1 + sum0_2;
//1
lookup1_1 <= look_A3_A0({DIN_8b_12[1],DIN_8b_13[1],DIN_8b_14[1],DIN[1]});
lookup1_2 <= look_A7_A4({DIN_8b_8[1],DIN_8b_9[1],DIN_8b_10[1],DIN_8b_11[1]});
lookup1_3 <= look_A7_A4({DIN_8b_7[1],DIN_8b_6[1],DIN_8b_5[1],DIN_8b_4[1]});
lookup1_4 <= look_A3_A0({DIN_8b_3[1],DIN_8b_2[1],DIN_8b_1[1],DIN_8b_0[1]});
sum1_1 <= lookup1_1 + lookup1_2;
sum1_2 <= lookup1_3 + lookup1_4;
sum1 <= sum1_1 + sum1_2;
//2
lookup2_1 <= look_A3_A0({DIN_8b_12[2],DIN_8b_13[2],DIN_8b_14[2],DIN[2]});
lookup2_2 <= look_A7_A4({DIN_8b_8[2],DIN_8b_9[2],DIN_8b_10[2],DIN_8b_11[2]});
lookup2_3 <= look_A7_A4({DIN_8b_7[2],DIN_8b_6[2],DIN_8b_5[2],DIN_8b_4[2]});
lookup2_4 <= look_A3_A0({DIN_8b_3[2],DIN_8b_2[2],DIN_8b_1[2],DIN_8b_0[2]});
sum2_1 <= lookup2_1 + lookup2_2;
sum2_2 <= lookup2_3 + lookup2_4;
sum2 <= sum2_1 + sum2_2;
//3
lookup3_1 <= look_A3_A0({DIN_8b_12[3],DIN_8b_13[3],DIN_8b_14[3],DIN[3]});
lookup3_2 <= look_A7_A4({DIN_8b_8[3],DIN_8b_9[3],DIN_8b_10[3],DIN_8b_11[3]});
lookup3_3 <= look_A7_A4({DIN_8b_7[3],DIN_8b_6[3],DIN_8b_5[3],DIN_8b_4[3]});
lookup3_4 <= look_A3_A0({DIN_8b_3[3],DIN_8b_2[3],DIN_8b_1[3],DIN_8b_0[3]});
sum3_1 <= lookup3_1 + lookup3_2;
sum3_2 <= lookup3_3 + lookup3_4;
sum3 <= sum3_1 + sum3_2;
//4
lookup4_1 <= look_A3_A0({DIN_8b_12[4],DIN_8b_13[4],DIN_8b_14[4],DIN[4]});
lookup4_2 <= look_A7_A4({DIN_8b_8[4],DIN_8b_9[4],DIN_8b_10[4],DIN_8b_11[4]});
lookup4_3 <= look_A7_A4({DIN_8b_7[4],DIN_8b_6[4],DIN_8b_5[4],DIN_8b_4[4]});
lookup4_4 <= look_A3_A0({DIN_8b_3[4],DIN_8b_2[4],DIN_8b_1[4],DIN_8b_0[4]});
sum4_1 <= lookup4_1 + lookup4_2;
sum4_2 <= lookup4_3 + lookup4_4;
sum4 <= sum4_1 + sum4_2;
//5
lookup5_1 <= look_A3_A0({DIN_8b_12[5],DIN_8b_13[5],DIN_8b_14[5],DIN[5]});
lookup5_2 <= look_A7_A4({DIN_8b_8[5],DIN_8b_9[5],DIN_8b_10[5],DIN_8b_11[5]});
lookup5_3 <= look_A7_A4({DIN_8b_7[5],DIN_8b_6[5],DIN_8b_5[5],DIN_8b_4[5]});
lookup5_4 <= look_A3_A0({DIN_8b_3[5],DIN_8b_2[5],DIN_8b_1[5],DIN_8b_0[5]});
sum5_1 <= lookup5_1 + lookup5_2;
sum5_2 <= lookup5_3 + lookup5_4;
sum5 <= sum5_1 + sum5_2;
//6
lookup6_1 <= look_A3_A0({DIN_8b_12[6],DIN_8b_13[6],DIN_8b_14[6],DIN[6]});
lookup6_2 <= look_A7_A4({DIN_8b_8[6],DIN_8b_9[6],DIN_8b_10[6],DIN_8b_11[6]});
lookup6_3 <= look_A7_A4({DIN_8b_7[6],DIN_8b_6[6],DIN_8b_5[6],DIN_8b_4[6]});
lookup6_4 <= look_A3_A0({DIN_8b_3[6],DIN_8b_2[6],DIN_8b_1[6],DIN_8b_0[6]});
sum6_1 <= lookup6_1 + lookup6_2;
sum6_2 <= lookup6_3 + lookup6_4;
sum6 <= sum6_1 + sum6_2;
//7
lookup7_1 <= look_A3_A0({DIN_8b_12[7],DIN_8b_13[7],DIN_8b_14[7],DIN[7]});
lookup7_2 <= look_A7_A4({DIN_8b_8[7],DIN_8b_9[7],DIN_8b_10[7],DIN_8b_11[7]});
lookup7_3 <= look_A7_A4({DIN_8b_7[7],DIN_8b_6[7],DIN_8b_5[7],DIN_8b_4[7]});
lookup7_4 <= look_A3_A0({DIN_8b_3[7],DIN_8b_2[7],DIN_8b_1[7],DIN_8b_0[7]});
sum7_1 <= lookup7_1 + lookup7_2;
sum7_2 <= lookup7_3 + lookup7_4;
sum7 <= sum7_1 + sum7_2;
end
else;
end
// 流水线加法
always @(posedge CLK or posedge Reset)
begin
if (Reset)
begin
temp_1_1 <= 0;
temp_1_2 <= 0;
temp_1_3 <= 0;
temp_1_4 <= 0;
temp_2_1 <= 0;
temp_2_2 <= 0;
temp_3 <= 0;
end
else
if(count_4b==15)
begin
temp_1_1 <= {{7{sum0[18]}},sum0} + {{6{sum1[18]}},sum1,1'b0};
temp_1_2 <= {{5{sum2[18]}},sum2,2'b0} + {{4{sum3[18]}},sum3,3'b0};
temp_1_3 <= {{3{sum4[18]}},sum4,4'b0} + {{2{sum5[18]}},sum5,5'b0};
temp_1_4 <= {sum6[18],sum6,6'b0}- {sum7,7'b0};
temp_2_1 <= temp_1_1 + temp_1_2;
temp_2_2 <= temp_1_3 + temp_1_4;
temp_3 <= temp_2_1 + temp_2_2 ;
end
else;
end
endmodule⌨️ 快捷键说明
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