📄 tb_fir.v
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`timescale 1ns / 1ps
module tb_fir();
// Input Signals
reg clock;
integer fopenok_stimuli;
reg SystemReset;
reg [15:0] ifir_ins;
integer ifir_ins_stimuli, ifir_ins_valinteger, aaaaa ;
// Output Signals
wire [15:0] ofir_outs;
integer ofir_outs_stimuli, ofir_outs_valinteger ;
initial
begin
fopenok_stimuli =1;
ifir_ins_stimuli = $fopen ("fir_in.salt","r");
if (ifir_ins_stimuli==0) fopenok_stimuli=0;
if (ifir_ins_stimuli==0) $display("unable to open input stimuli files fir_in.salt");
ofir_outs_stimuli = $fopen ("fir_out.txt");
if (ofir_outs_stimuli==0) fopenok_stimuli=0;
if (ofir_outs_stimuli==0) $display("unable to open output stimuli files fir_out.txt");
#0 clock = 1'b0;
#0 SystemReset = 1'b1;
#80 SystemReset = 1'b0;
end
always
begin
#10.000 clock = 1;
#10.000 clock = 0;
end
// Read input stimuli from ifir_ins.salt file
always @(negedge clock)
begin
if ((SystemReset==0)&&(fopenok_stimuli==1))
begin
aaaaa = $fscanf(ifir_ins_stimuli,"%d",ifir_ins_valinteger);
//$fread(ifir_ins_stimuli,"%d",ifir_ins_valinteger);
ifir_ins <= ifir_ins_valinteger;
end
end
// Write output results ofir_outsin ofir_outs.txt file
always @(negedge clock)
begin
if ((SystemReset==0)&&(fopenok_stimuli==1))
begin
ofir_outs_valinteger = ofir_outs;
$fdisplay(ofir_outs_stimuli,"%d",(ofir_outs_valinteger<32768)?ofir_outs_valinteger:ofir_outs_valinteger-65536);
end
end
initial
#9000 $stop;
// Insert your code here with instance name 'dut' (Device under test)
firfilter_da dut(.CLK (clock ),
.Reset (SystemReset ),
.DIN (ifir_ins[15:8] ),
.Dout (ofir_outs ));
endmodule
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