firfilter_da.fit.summary

分布式算法在实现乘加功能时

Fitter Status : Successful - Mon Nov 26 20:36:55 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : firfilter_da
Top-level Entity Name : firfilter_da
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 8 %
    Combinational ALUTs : 915 / 12,480 ( 7 % )
    Dedicated logic registers : 1,007 / 12,480 ( 8 % )
Total registers : 1007
Total pins : 26 / 343 ( 8 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )