firfilter.map.qmsg

实现一个FIR滤波器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 18:38:04 2007 " "Info: Processing started: Mon Nov 26 18:38:04 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off firfilter -c firfilter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off firfilter -c firfilter" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file mult.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult " "Info: Found entity 1: mult" {  } { { "mult.v" "" { Text "E:/firfilter/mult.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(73) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(73): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 73 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(74) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(74): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 74 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(75) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(75): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 75 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(76) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(76): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 76 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(77) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(77): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 77 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(78) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(78): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 78 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(79) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(79): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 79 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 firfilter.v(80) " "Warning (10229): Verilog HDL Expression warning at firfilter.v(80): truncated literal to match 16 bits" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 80 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "firfilter.v(85) " "Warning (10268): Verilog HDL information at firfilter.v(85): Always Construct contains both blocking and non-blocking assignments" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 85 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "firfilter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file firfilter.v" { { "Info" "ISGN_ENTITY_NAME" "1 firfilter " "Info: Found entity 1: firfilter" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "firfilter " "Info: Elaborating entity \"firfilter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}