prev_cmp_firfilter.tan.qmsg

实现一个FIR滤波器

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Dout\[8\] result_28b\[19\] 6.375 ns register " "Info: tco from clock \"CLK\" to destination pin \"Dout\[8\]\" through register \"result_28b\[19\]\" is 6.375 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.457 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.457 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1022 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1022; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.642 ns) + CELL(0.618 ns) 2.457 ns result_28b\[19\] 3 REG LCFF_X14_Y9_N7 1 " "Info: 3: + IC(0.642 ns) + CELL(0.618 ns) = 2.457 ns; Loc. = LCFF_X14_Y9_N7; Fanout = 1; REG Node = 'result_28b\[19\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.260 ns" { CLK~clkctrl result_28b[19] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 366 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.91 % ) " "Info: Total cell delay = 1.472 ns ( 59.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 40.09 % ) " "Info: Total interconnect delay = 0.985 ns ( 40.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.457 ns" { CLK CLK~clkctrl result_28b[19] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.457 ns" { CLK CLK~combout CLK~clkctrl result_28b[19] } { 0.000ns 0.000ns 0.343ns 0.642ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 366 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.824 ns + Longest register pin " "Info: + Longest register to pin delay is 3.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns result_28b\[19\] 1 REG LCFF_X14_Y9_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y9_N7; Fanout = 1; REG Node = 'result_28b\[19\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { result_28b[19] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 366 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.680 ns) + CELL(2.144 ns) 3.824 ns Dout\[8\] 2 PIN PIN_L20 0 " "Info: 2: + IC(1.680 ns) + CELL(2.144 ns) = 3.824 ns; Loc. = PIN_L20; Fanout = 0; PIN Node = 'Dout\[8\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.824 ns" { result_28b[19] Dout[8] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.144 ns ( 56.07 % ) " "Info: Total cell delay = 2.144 ns ( 56.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.680 ns ( 43.93 % ) " "Info: Total interconnect delay = 1.680 ns ( 43.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.824 ns" { result_28b[19] Dout[8] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "3.824 ns" { result_28b[19] Dout[8] } { 0.000ns 1.680ns } { 0.000ns 2.144ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.457 ns" { CLK CLK~clkctrl result_28b[19] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.457 ns" { CLK CLK~combout CLK~clkctrl result_28b[19] } { 0.000ns 0.000ns 0.343ns 0.642ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.824 ns" { result_28b[19] Dout[8] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "3.824 ns" { result_28b[19] Dout[8] } { 0.000ns 1.680ns } { 0.000ns 2.144ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "Din_8b_10\[5\] DIN\[5\] CLK -2.457 ns register " "Info: th for register \"Din_8b_10\[5\]\" (data pin = \"DIN\[5\]\", clock pin = \"CLK\") is -2.457 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.456 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1022 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1022; COMB Node = 'CLK~clkctrl'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.641 ns) + CELL(0.618 ns) 2.456 ns Din_8b_10\[5\] 3 REG LCFF_X15_Y8_N25 3 " "Info: 3: + IC(0.641 ns) + CELL(0.618 ns) = 2.456 ns; Loc. = LCFF_X15_Y8_N25; Fanout = 3; REG Node = 'Din_8b_10\[5\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { CLK~clkctrl Din_8b_10[5] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.93 % ) " "Info: Total cell delay = 1.472 ns ( 59.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.984 ns ( 40.07 % ) " "Info: Total interconnect delay = 0.984 ns ( 40.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.456 ns" { CLK CLK~clkctrl Din_8b_10[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.456 ns" { CLK CLK~combout CLK~clkctrl Din_8b_10[5] } { 0.000ns 0.000ns 0.343ns 0.641ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 148 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.062 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.062 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns DIN\[5\] 1 PIN PIN_P19 17 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_P19; Fanout = 17; PIN Node = 'DIN\[5\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN[5] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.943 ns) + CELL(0.309 ns) 5.062 ns Din_8b_10\[5\] 2 REG LCFF_X15_Y8_N25 3 " "Info: 2: + IC(3.943 ns) + CELL(0.309 ns) = 5.062 ns; Loc. = LCFF_X15_Y8_N25; Fanout = 3; REG Node = 'Din_8b_10\[5\]'" {  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.252 ns" { DIN[5] Din_8b_10[5] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.119 ns ( 22.11 % ) " "Info: Total cell delay = 1.119 ns ( 22.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.943 ns ( 77.89 % ) " "Info: Total interconnect delay = 3.943 ns ( 77.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.062 ns" { DIN[5] Din_8b_10[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "5.062 ns" { DIN[5] DIN[5]~combout Din_8b_10[5] } { 0.000ns 0.000ns 3.943ns } { 0.000ns 0.810ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.456 ns" { CLK CLK~clkctrl Din_8b_10[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.456 ns" { CLK CLK~combout CLK~clkctrl Din_8b_10[5] } { 0.000ns 0.000ns 0.343ns 0.641ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.062 ns" { DIN[5] Din_8b_10[5] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "5.062 ns" { DIN[5] DIN[5]~combout Din_8b_10[5] } { 0.000ns 0.000ns 3.943ns } { 0.000ns 0.810ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 18:38:44 2007 " "Info: Processing ended: Mon Nov 26 18:38:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}