📄 prev_cmp_firfilter.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } { "d:/eda/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/eda/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register mult_28b_3\[2\] register sum_28b_21\[27\] 298.95 MHz 3.345 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 298.95 MHz between source register \"mult_28b_3\[2\]\" and destination register \"sum_28b_21\[27\]\" (period= 3.345 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.115 ns + Longest register register " "Info: + Longest register to register delay is 3.115 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.580 ns) 0.580 ns mult_28b_3\[2\] 1 REG DSPOUT_X12_Y11_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.580 ns) = 0.580 ns; Loc. = DSPOUT_X12_Y11_N2; Fanout = 2; REG Node = 'mult_28b_3\[2\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { mult_28b_3[2] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 268 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.947 ns) + CELL(0.309 ns) 1.836 ns Add10~426 2 COMB LCCOMB_X11_Y10_N4 2 " "Info: 2: + IC(0.947 ns) + CELL(0.309 ns) = 1.836 ns; Loc. = LCCOMB_X11_Y10_N4; Fanout = 2; COMB Node = 'Add10~426'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { mult_28b_3[2] Add10~426 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 1.871 ns Add10~430 3 COMB LCCOMB_X11_Y10_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 1.871 ns; Loc. = LCCOMB_X11_Y10_N6; Fanout = 2; COMB Node = 'Add10~430'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~426 Add10~430 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 1.906 ns Add10~434 4 COMB LCCOMB_X11_Y10_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 1.906 ns; Loc. = LCCOMB_X11_Y10_N8; Fanout = 2; COMB Node = 'Add10~434'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~430 Add10~434 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 1.941 ns Add10~438 5 COMB LCCOMB_X11_Y10_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 1.941 ns; Loc. = LCCOMB_X11_Y10_N10; Fanout = 2; COMB Node = 'Add10~438'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~434 Add10~438 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 1.976 ns Add10~442 6 COMB LCCOMB_X11_Y10_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 1.976 ns; Loc. = LCCOMB_X11_Y10_N12; Fanout = 2; COMB Node = 'Add10~442'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~438 Add10~442 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.072 ns Add10~446 7 COMB LCCOMB_X11_Y10_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.096 ns) = 2.072 ns; Loc. = LCCOMB_X11_Y10_N14; Fanout = 2; COMB Node = 'Add10~446'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Add10~442 Add10~446 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.107 ns Add10~450 8 COMB LCCOMB_X11_Y10_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 2.107 ns; Loc. = LCCOMB_X11_Y10_N16; Fanout = 2; COMB Node = 'Add10~450'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~446 Add10~450 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.142 ns Add10~454 9 COMB LCCOMB_X11_Y10_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.035 ns) = 2.142 ns; Loc. = LCCOMB_X11_Y10_N18; Fanout = 2; COMB Node = 'Add10~454'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~450 Add10~454 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.177 ns Add10~458 10 COMB LCCOMB_X11_Y10_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 2.177 ns; Loc. = LCCOMB_X11_Y10_N20; Fanout = 2; COMB Node = 'Add10~458'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~454 Add10~458 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.212 ns Add10~462 11 COMB LCCOMB_X11_Y10_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 2.212 ns; Loc. = LCCOMB_X11_Y10_N22; Fanout = 2; COMB Node = 'Add10~462'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~458 Add10~462 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.247 ns Add10~466 12 COMB LCCOMB_X11_Y10_N24 2 " "Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 2.247 ns; Loc. = LCCOMB_X11_Y10_N24; Fanout = 2; COMB Node = 'Add10~466'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~462 Add10~466 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.282 ns Add10~470 13 COMB LCCOMB_X11_Y10_N26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.035 ns) = 2.282 ns; Loc. = LCCOMB_X11_Y10_N26; Fanout = 2; COMB Node = 'Add10~470'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~466 Add10~470 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.317 ns Add10~474 14 COMB LCCOMB_X11_Y10_N28 2 " "Info: 14: + IC(0.000 ns) + CELL(0.035 ns) = 2.317 ns; Loc. = LCCOMB_X11_Y10_N28; Fanout = 2; COMB Node = 'Add10~474'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~470 Add10~474 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.517 ns Add10~478 15 COMB LCCOMB_X11_Y10_N30 2 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 2.517 ns; Loc. = LCCOMB_X11_Y10_N30; Fanout = 2; COMB Node = 'Add10~478'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { Add10~474 Add10~478 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.552 ns Add10~482 16 COMB LCCOMB_X11_Y9_N0 2 " "Info: 16: + IC(0.000 ns) + CELL(0.035 ns) = 2.552 ns; Loc. = LCCOMB_X11_Y9_N0; Fanout = 2; COMB Node = 'Add10~482'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~478 Add10~482 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.587 ns Add10~486 17 COMB LCCOMB_X11_Y9_N2 2 " "Info: 17: + IC(0.000 ns) + CELL(0.035 ns) = 2.587 ns; Loc. = LCCOMB_X11_Y9_N2; Fanout = 2; COMB Node = 'Add10~486'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~482 Add10~486 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.622 ns Add10~490 18 COMB LCCOMB_X11_Y9_N4 2 " "Info: 18: + IC(0.000 ns) + CELL(0.035 ns) = 2.622 ns; Loc. = LCCOMB_X11_Y9_N4; Fanout = 2; COMB Node = 'Add10~490'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~486 Add10~490 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.657 ns Add10~494 19 COMB LCCOMB_X11_Y9_N6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.035 ns) = 2.657 ns; Loc. = LCCOMB_X11_Y9_N6; Fanout = 2; COMB Node = 'Add10~494'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~490 Add10~494 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.692 ns Add10~498 20 COMB LCCOMB_X11_Y9_N8 2 " "Info: 20: + IC(0.000 ns) + CELL(0.035 ns) = 2.692 ns; Loc. = LCCOMB_X11_Y9_N8; Fanout = 2; COMB Node = 'Add10~498'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~494 Add10~498 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.727 ns Add10~502 21 COMB LCCOMB_X11_Y9_N10 2 " "Info: 21: + IC(0.000 ns) + CELL(0.035 ns) = 2.727 ns; Loc. = LCCOMB_X11_Y9_N10; Fanout = 2; COMB Node = 'Add10~502'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~498 Add10~502 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.762 ns Add10~506 22 COMB LCCOMB_X11_Y9_N12 2 " "Info: 22: + IC(0.000 ns) + CELL(0.035 ns) = 2.762 ns; Loc. = LCCOMB_X11_Y9_N12; Fanout = 2; COMB Node = 'Add10~506'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~502 Add10~506 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.858 ns Add10~510 23 COMB LCCOMB_X11_Y9_N14 2 " "Info: 23: + IC(0.000 ns) + CELL(0.096 ns) = 2.858 ns; Loc. = LCCOMB_X11_Y9_N14; Fanout = 2; COMB Node = 'Add10~510'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Add10~506 Add10~510 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 2.893 ns Add10~514 24 COMB LCCOMB_X11_Y9_N16 1 " "Info: 24: + IC(0.000 ns) + CELL(0.035 ns) = 2.893 ns; Loc. = LCCOMB_X11_Y9_N16; Fanout = 1; COMB Node = 'Add10~514'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { Add10~510 Add10~514 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 3.018 ns Add10~517 25 COMB LCCOMB_X11_Y9_N18 1 " "Info: 25: + IC(0.000 ns) + CELL(0.125 ns) = 3.018 ns; Loc. = LCCOMB_X11_Y9_N18; Fanout = 1; COMB Node = 'Add10~517'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add10~514 Add10~517 } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 331 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.097 ns) 3.115 ns sum_28b_21\[27\] 26 REG LCFF_X11_Y9_N19 3 " "Info: 26: + IC(0.000 ns) + CELL(0.097 ns) = 3.115 ns; Loc. = LCFF_X11_Y9_N19; Fanout = 3; REG Node = 'sum_28b_21\[27\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.097 ns" { Add10~517 sum_28b_21[27] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 323 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.168 ns ( 69.60 % ) " "Info: Total cell delay = 2.168 ns ( 69.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.947 ns ( 30.40 % ) " "Info: Total interconnect delay = 0.947 ns ( 30.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.115 ns" { mult_28b_3[2] Add10~426 Add10~430 Add10~434 Add10~438 Add10~442 Add10~446 Add10~450 Add10~454 Add10~458 Add10~462 Add10~466 Add10~470 Add10~474 Add10~478 Add10~482 Add10~486 Add10~490 Add10~494 Add10~498 Add10~502 Add10~506 Add10~510 Add10~514 Add10~517 sum_28b_21[27] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "3.115 ns" { mult_28b_3[2] Add10~426 Add10~430 Add10~434 Add10~438 Add10~442 Add10~446 Add10~450 Add10~454 Add10~458 Add10~462 Add10~466 Add10~470 Add10~474 Add10~478 Add10~482 Add10~486 Add10~490 Add10~494 Add10~498 Add10~502 Add10~506 Add10~510 Add10~514 Add10~517 sum_28b_21[27] } { 0.000ns 0.947ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.580ns 0.309ns 0.035ns 0.035ns 0.035ns 0.035ns 0.096ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.200ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.096ns 0.035ns 0.125ns 0.097ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.140 ns - Smallest " "Info: - Smallest clock skew is -0.140 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.485 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1022 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1022; COMB Node = 'CLK~clkctrl'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.485 ns sum_28b_21\[27\] 3 REG LCFF_X11_Y9_N19 3 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X11_Y9_N19; Fanout = 3; REG Node = 'sum_28b_21\[27\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { CLK~clkctrl sum_28b_21[27] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 323 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.24 % ) " "Info: Total cell delay = 1.472 ns ( 59.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.76 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl sum_28b_21[27] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK CLK~combout CLK~clkctrl sum_28b_21[27] } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.625 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.625 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1022 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1022; COMB Node = 'CLK~clkctrl'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.780 ns) 2.625 ns mult_28b_3\[2\] 3 REG DSPOUT_X12_Y11_N2 2 " "Info: 3: + IC(0.648 ns) + CELL(0.780 ns) = 2.625 ns; Loc. = DSPOUT_X12_Y11_N2; Fanout = 2; REG Node = 'mult_28b_3\[2\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.428 ns" { CLK~clkctrl mult_28b_3[2] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 268 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns ( 62.25 % ) " "Info: Total cell delay = 1.634 ns ( 62.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 37.75 % ) " "Info: Total interconnect delay = 0.991 ns ( 37.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { CLK CLK~clkctrl mult_28b_3[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { CLK CLK~combout CLK~clkctrl mult_28b_3[2] } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.780ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl sum_28b_21[27] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK CLK~combout CLK~clkctrl sum_28b_21[27] } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { CLK CLK~clkctrl mult_28b_3[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { CLK CLK~combout CLK~clkctrl mult_28b_3[2] } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.780ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 268 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 323 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.115 ns" { mult_28b_3[2] Add10~426 Add10~430 Add10~434 Add10~438 Add10~442 Add10~446 Add10~450 Add10~454 Add10~458 Add10~462 Add10~466 Add10~470 Add10~474 Add10~478 Add10~482 Add10~486 Add10~490 Add10~494 Add10~498 Add10~502 Add10~506 Add10~510 Add10~514 Add10~517 sum_28b_21[27] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "3.115 ns" { mult_28b_3[2] Add10~426 Add10~430 Add10~434 Add10~438 Add10~442 Add10~446 Add10~450 Add10~454 Add10~458 Add10~462 Add10~466 Add10~470 Add10~474 Add10~478 Add10~482 Add10~486 Add10~490 Add10~494 Add10~498 Add10~502 Add10~506 Add10~510 Add10~514 Add10~517 sum_28b_21[27] } { 0.000ns 0.947ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.580ns 0.309ns 0.035ns 0.035ns 0.035ns 0.035ns 0.096ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.200ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.096ns 0.035ns 0.125ns 0.097ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { CLK CLK~clkctrl sum_28b_21[27] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { CLK CLK~combout CLK~clkctrl sum_28b_21[27] } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.625 ns" { CLK CLK~clkctrl mult_28b_3[2] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.625 ns" { CLK CLK~combout CLK~clkctrl mult_28b_3[2] } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.780ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Din_8b_12\[4\] DIN\[4\] CLK 3.629 ns register " "Info: tsu for register \"Din_8b_12\[4\]\" (data pin = \"DIN\[4\]\", clock pin = \"CLK\") is 3.629 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.005 ns + Longest pin register " "Info: + Longest pin to register delay is 6.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.837 ns) 0.837 ns DIN\[4\] 1 PIN PIN_W13 17 " "Info: 1: + IC(0.000 ns) + CELL(0.837 ns) = 0.837 ns; Loc. = PIN_W13; Fanout = 17; PIN Node = 'DIN\[4\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DIN[4] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.859 ns) + CELL(0.309 ns) 6.005 ns Din_8b_12\[4\] 2 REG LCFF_X17_Y11_N29 3 " "Info: 2: + IC(4.859 ns) + CELL(0.309 ns) = 6.005 ns; Loc. = LCFF_X17_Y11_N29; Fanout = 3; REG Node = 'Din_8b_12\[4\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.168 ns" { DIN[4] Din_8b_12[4] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.146 ns ( 19.08 % ) " "Info: Total cell delay = 1.146 ns ( 19.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.859 ns ( 80.92 % ) " "Info: Total interconnect delay = 4.859 ns ( 80.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.005 ns" { DIN[4] Din_8b_12[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "6.005 ns" { DIN[4] DIN[4]~combout Din_8b_12[4] } { 0.000ns 0.000ns 4.859ns } { 0.000ns 0.837ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 148 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.466 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.466 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 1022 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 1022; COMB Node = 'CLK~clkctrl'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.651 ns) + CELL(0.618 ns) 2.466 ns Din_8b_12\[4\] 3 REG LCFF_X17_Y11_N29 3 " "Info: 3: + IC(0.651 ns) + CELL(0.618 ns) = 2.466 ns; Loc. = LCFF_X17_Y11_N29; Fanout = 3; REG Node = 'Din_8b_12\[4\]'" { } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.269 ns" { CLK~clkctrl Din_8b_12[4] } "NODE_NAME" } } { "firfilter.v" "" { Text "E:/firfilter/firfilter.v" 148 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.69 % ) " "Info: Total cell delay = 1.472 ns ( 59.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 40.31 % ) " "Info: Total interconnect delay = 0.994 ns ( 40.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { CLK CLK~clkctrl Din_8b_12[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { CLK CLK~combout CLK~clkctrl Din_8b_12[4] } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.005 ns" { DIN[4] Din_8b_12[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "6.005 ns" { DIN[4] DIN[4]~combout Din_8b_12[4] } { 0.000ns 0.000ns 4.859ns } { 0.000ns 0.837ns 0.309ns } "" } } { "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { CLK CLK~clkctrl Din_8b_12[4] } "NODE_NAME" } } { "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/altera/71/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { CLK CLK~combout CLK~clkctrl Din_8b_12[4] } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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