firfilter.fit.summary

实现一个FIR滤波器

Fitter Status : Successful - Mon Nov 26 18:38:25 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : firfilter
Top-level Entity Name : firfilter
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : 3 %
    Combinational ALUTs : 278 / 12,480 ( 2 % )
    Dedicated logic registers : 370 / 12,480 ( 3 % )
Total registers : 370
Total pins : 26 / 343 ( 8 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 16 / 96 ( 17 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )