firfilter.v

实现一个FIR滤波器

//////////////////////////////////////////////////////////////////
//                                                              //
// Copyright(c) :  2007,EDA,PHY,WHU                             //
//                                                              //
//--------------------------------------------------------------//
// FILE NAME    :  firfilter.v                                  //
// TYPE         :  module                                       //
// AUTHOR       :  Eric.Hui.Shao                                //
// EMAIL@       :  [e-mail]                             //
//--------------------------------------------------------------//
// Purpose      :  FIR direct filter                						//
// Assumptions  :  none                                         //
// Limitations  :  none                                         //
// Known Errors :  none                                         //
// Notes        :   (16 steps)                                  //
//              :                                               //
//--------------------------------------------------------------//
// Release history                                              //
// 1.0 25th November 2007 initial version                       //
//                                                              //
//////////////////////////////////////////////////////////////////

//-----------------------
//  module description
//-----------------------
module firfilter(CLK,
				  Reset,
				  DIN,
				  Dout);
//-----------------------
//  port declaration
//-----------------------
	input	CLK;
	input	Reset;
	input	[7:0]	DIN;
	output	[15:0] 	Dout;

//输入信号寄存器	
	reg [7:0]	Din_8b_0;
	reg [7:0]	Din_8b_1;
	reg [7:0]	Din_8b_2;
	reg [7:0]	Din_8b_3;
	reg [7:0]	Din_8b_4;
	reg	[7:0] 	Din_8b_5;
	reg [7:0] 	Din_8b_6;
	reg [7:0] 	Din_8b_7;
	reg [7:0] 	Din_8b_8;
	reg [7:0] 	Din_8b_9;
	reg [7:0] 	Din_8b_10;
	reg [7:0] 	Din_8b_11;
	reg [7:0] 	Din_8b_12;
	reg [7:0] 	Din_8b_13;
	reg [7:0] 	Din_8b_14;

//首尾对称两项和，经过高位扩展，一级加法和寄存器	
	reg [8:0]	sum_9b_0;
	reg [8:0]	sum_9b_1;
	reg [8:0]	sum_9b_2;
	reg [8:0]	sum_9b_3;
	reg [8:0]	sum_9b_4;
	reg [8:0]	sum_9b_5;
	reg [8:0]	sum_9b_6;
	reg [8:0]	sum_9b_7;

//一级加法和与系数相乘结果寄存器	
	wire [24:0] mult_25b_0;
	wire [24:0] mult_25b_1;
	wire [24:0] mult_25b_2;
	wire [24:0] mult_25b_3;
	wire [24:0] mult_25b_4;
	wire [24:0] mult_25b_5;
	wire [24:0] mult_25b_6;
	wire [24:0] mult_25b_7;
	
	reg [27:0] mult_28b_0;
	reg [27:0] mult_28b_1;
	reg [27:0] mult_28b_2;
	reg [27:0] mult_28b_3;
	reg [27:0] mult_28b_4;
	reg [27:0] mult_28b_5;
	reg [27:0] mult_28b_6;
	reg [27:0] mult_28b_7;

//二级加法和寄存器	
	reg [27:0] sum_28b_20;
	reg [27:0] sum_28b_21;
	reg [27:0] sum_28b_22;
	reg [27:0] sum_28b_23;

//三级加法和寄存器	
	reg [27:0] sum_28b_30;
	reg [27:0] sum_28b_31;

//最终结果寄存器	
	reg	[27:0] result_28b;
	
//输出信号设定
	wire	[15:0]	Dout;
	assign Dout={result_28b[27],result_28b[25:11]};

//信号计数器
	reg	[3:0]	count_4b;

//16阶滤波器抽头系数	
	parameter	H_16b_0=16'H_16b_0000;
	parameter	H_16b_1=16'H_16b_0065;
	parameter	H_16b_2=16'H_16b_018F;
	parameter	H_16b_3=16'H_16b_035A;
	parameter	H_16b_4=16'H_16b_0579;
	parameter	H_16b_5=16'H_16b_078E;
	parameter	H_16b_6=16'H_16b_0935;
	parameter	H_16b_7=16'H_16b_0A1F;
	


// 输入信号的初始化
always @(posedge CLK or posedge Reset)
begin
	if(Reset)
	  begin
		count_4b<=0;
		Din_8b_0<=0;
		Din_8b_1<=0;
		Din_8b_2<=0;
		Din_8b_3<=0;
		Din_8b_4<=0;
		Din_8b_5<=0;
		Din_8b_6<=0;
		Din_8b_7<=0;
		Din_8b_8<=0;
		Din_8b_9<=0;
		Din_8b_10<=0;
		Din_8b_11<=0;
		Din_8b_12<=0;
		Din_8b_13<=0;
		Din_8b_14<=0;
	  end
	else
	  begin
		if(count_4b==15)
		  begin
			Din_8b_0<=Din_8b_1;
			Din_8b_1<=Din_8b_2;
			Din_8b_2<=Din_8b_3;
			Din_8b_3<=Din_8b_4;
			Din_8b_4<=Din_8b_5;
			Din_8b_5<=Din_8b_6;
			Din_8b_6<=Din_8b_7;
			Din_8b_7<=Din_8b_8;
			Din_8b_8<=Din_8b_9;
			Din_8b_9<=Din_8b_10;
			Din_8b_10<=Din_8b_11;
			Din_8b_11<=Din_8b_12;
			Din_8b_12<=Din_8b_13;
			Din_8b_13<=Din_8b_14;
			Din_8b_14<=DIN;
		  end
		else	
		  begin
		  case(count_4b)
			'd0: Din_8b_0=DIN;
			'd1: Din_8b_1=DIN;
			'd2: Din_8b_2=DIN;
			'd3: Din_8b_3=DIN;			
			'd4: Din_8b_4=DIN;
			'd5: Din_8b_5=DIN;
			'd6: Din_8b_6=DIN;
			'd7: Din_8b_7=DIN;
			'd8: Din_8b_8=DIN;
			'd9: Din_8b_9=DIN;
			'd10: Din_8b_10=DIN;
			'd11: Din_8b_11=DIN;
			'd12: Din_8b_12=DIN;
			'd13: Din_8b_13=DIN;
			'd14: Din_8b_14=DIN;
			default:;
		  endcase
		  	count_4b=count_4b+1;			
		  end
	  end
end

//一级加法单元
always @(posedge CLK or posedge Reset)
begin
	if(Reset)
		begin
			sum_9b_0 <= 0;
			sum_9b_1 <= 0;
			sum_9b_2 <= 0;
			sum_9b_3 <= 0;
			sum_9b_4 <= 0;
			sum_9b_5 <= 0;
			sum_9b_6 <= 0;
			sum_9b_7 <= 0;
		end
	else
		if(count_4b==15)
			begin
				sum_9b_0 <= {Din_8b_0[7],Din_8b_0} + {DIN[7],DIN};
				sum_9b_1 <= {Din_8b_1[7],Din_8b_1} + {Din_8b_14[7],Din_8b_14};
				sum_9b_2 <= {Din_8b_2[7],Din_8b_2} + {Din_8b_13[7],Din_8b_13};
				sum_9b_3 <= {Din_8b_3[7],Din_8b_3} + {Din_8b_12[7],Din_8b_12};
				sum_9b_4 <= {Din_8b_4[7],Din_8b_4} + {Din_8b_11[7],Din_8b_11};
				sum_9b_5 <= {Din_8b_5[7],Din_8b_5} + {Din_8b_10[7],Din_8b_10};
				sum_9b_6 <= {Din_8b_6[7],Din_8b_6} + {Din_8b_9[7],Din_8b_9};
				sum_9b_7 <= {Din_8b_7[7],Din_8b_7} + {Din_8b_8[7],Din_8b_8};
			end
		else;
end

//乘法单元                       
  mult mult_0(
              //input
              .clock(CLK),
              .dataa(H_16b_0),
              .datab(sum_9b_0),
              //output
              .result(mult_25b_0)
              );
  
  mult mult_1(
              //input
              .clock(CLK),
              .dataa(H_16b_1),
              .datab(sum_9b_1),
              //output
              .result(mult_25b_1)
              );
  
  mult mult_2(
              //input
              .clock(CLK),
              .dataa(H_16b_2),
              .datab(sum_9b_2),
              //output
              .result(mult_25b_2)
              );              

  mult mult_3(
              //input
              .clock(CLK),
              .dataa(H_16b_3),
              .datab(sum_9b_3),
              //output
              .result(mult_25b_3)
              );              

  mult mult_4(
              //input
              .clock(CLK),
              .dataa(H_16b_4),
              .datab(sum_9b_4),
              //output
              .result(mult_25b_4)
              );

  mult mult_5(
              //input
              .clock(CLK),
              .dataa(H_16b_5),
              .datab(sum_9b_5),
              //output
              .result(mult_25b_5)
              );

  mult mult_6(
              //input
              .clock(CLK),
              .dataa(H_16b_6),
              .datab(sum_9b_6),
              //output
              .result(mult_25b_6)
              );

  mult mult_7(
              //input
              .clock(CLK),
              .dataa(H_16b_7),
              .datab(sum_9b_7),
              //output
              .result(mult_25b_7)
              );

always @(posedge CLK or posedge Reset)
begin
	if(Reset)
		begin
			mult_28b_0 <= 0;
			mult_28b_1 <= 0;
			mult_28b_2 <= 0;
			mult_28b_3 <= 0;
			mult_28b_4 <= 0;
			mult_28b_5 <= 0;
			mult_28b_6 <= 0;
			mult_28b_7 <= 0;
		end
	else
		if(count_4b==15)
			begin
				mult_28b_0	<=	{{3{mult_25b_0[24]}}, mult_25b_0};
				mult_28b_1	<=	{{3{mult_25b_1[24]}}, mult_25b_1};
				mult_28b_2	<=	{{3{mult_25b_2[24]}}, mult_25b_2};
				mult_28b_3	<=	{{3{mult_25b_3[24]}}, mult_25b_3};
				mult_28b_4	<=	{{3{mult_25b_4[24]}}, mult_25b_4};
				mult_28b_5	<=	{{3{mult_25b_5[24]}}, mult_25b_5};
				mult_28b_6	<=	{{3{mult_25b_6[24]}}, mult_25b_6};
				mult_28b_7	<=	{{3{mult_25b_7[24]}}, mult_25b_7};
			end
		else;
end


//二级加法单元
always @(posedge CLK or posedge Reset)
begin
	if(Reset)
		begin
			sum_28b_20 <= 0;
			sum_28b_21 <= 0;
			sum_28b_22 <= 0;
			sum_28b_23 <= 0;
		end
	else
		if(count_4b==15)
			begin
				sum_28b_20 <= mult_28b_0 + mult_28b_1;
				sum_28b_21 <= mult_28b_2 + mult_28b_3;
				sum_28b_22 <= mult_28b_4 + mult_28b_5;
				sum_28b_23 <= mult_28b_6 + mult_28b_7;
			end
		else;
end

//三级加法单元
always @(posedge CLK or posedge Reset)
begin
	if(Reset)
		begin
			sum_28b_30 <= 0;
			sum_28b_31 <= 0;
		end
	else
		if(count_4b==15)
			begin
				sum_28b_30 <= sum_28b_20 + sum_28b_21;
				sum_28b_31 <= sum_28b_22 + sum_28b_23;
			end
		else;
end			

//最终结果，四级加法单元
always @(posedge CLK or posedge Reset)
begin
	if(Reset)
		begin
			result_28b <= 0;
		end
	else
		if(count_4b==15)
			begin
				result_28b <= sum_28b_30 + sum_28b_31;
			end
		else;
end

endmodule