_primary.vhd

来自「实现一个FIR滤波器」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity firfilter is
    generic(
        H_16b_0         : integer := 0;
        H_16b_1         : integer := 101;
        H_16b_2         : integer := 399;
        H_16b_3         : integer := 858;
        H_16b_4         : integer := 1401;
        H_16b_5         : integer := 1934;
        H_16b_6         : integer := 2357;
        H_16b_7         : integer := 2591
    );
    port(
        CLK             : in     vl_logic;
        Reset           : in     vl_logic;
        DIN             : in     vl_logic_vector(7 downto 0);
        Dout            : out    vl_logic_vector(15 downto 0)
    );
end firfilter;