cic_inter.v.bak

verilog码写的CIC滤波器的程序

/***********************************************************
cic filter,insert
***********************************************************/
module cic_inter(clk,clk_inter,rst,nd,cic_in,cic_out,decimator3_z,
                 integrator1,integrator2,integrator3,integrator4,integrator5,
                 decimator1,decimator2,decimator3,decimator4,decimator5,rdy);
    input clk;
    input clk_inter;
    input rst;
    input nd;       //nd=1,updata input signal
    input [15:0]cic_in;
    output [39:0]cic_out;
    output [39:0]decimator3_z;
    output rdy;
    output [39:0]integrator1,integrator2,integrator3,integrator4,integrator5;
    output [39:0]decimator1,decimator2,decimator3,decimator4,decimator5;
    
    reg [39:0]cic=0;
    reg [39:0]integrator1=0,
              integrator2=0,
              integrator3=0,
              integrator4=0,
              integrator5=0;
    reg [39:0]decimator1=0,
              decimator1_z=0,
              decimator2=0,
              decimator2_z=0,
              decimator3=0,
              decimator3_z=0,
              decimator4=0,
              decimator4_z=0,
              decimator5=0,
              decimator5_z=0;
    reg [39:0]cic_out=0;
    reg rdy;
    reg [7:0]counter=0;
    reg flag;
    
    always @(posedge clk or negedge rst)begin
        if(!rst)begin
        cic<=0;
        counter<=0;
        decimator1<=0;
        decimator1_z<=0;
        decimator2<=0;
        decimator2_z<=0;
        decimator3<=0;
        decimator3_z<=0;
        decimator4<=0;
        decimator4_z<=0;
        decimator5<=0;
        decimator5_z<=0;
    end
    else if(nd)
    begin
        decimator1[39:16]<={24{cic_in[15]}};
        decimator1[15:0]<=cic_in[15:0];
        decimator1_z<=decimator1;
        decimator2<=decimator1-decimator1_z;
        decimator2_z<=decimator2;
        decimator3<=decimator2-decimator2_z;
        decimator3_z<=decimator3;
        decimator4<=decimator3-decimator3_z;
        decimator4_z<=decimator4;
        //decimator5<=decimator4-decimator4_z;
        //decimator5_z<=decimator5;
    end
    else begin
        decimator4_z<=0;
    end
end

always @(posedge clk)begin
    counter<=counter+1;
    if(counter==4)
    begin
        counter<=0;
        integrator1<=decimator4_z+integrator1;
        integrator2<=integrator1+integrator2;
        integrator3<=integrator2+integrator3;
        cic_out<=integrator3;
        rdy<=1;
    end
    if(rdy)begin
        rdy<=0;
    end
end
endmodule