_primary.vhd

来自「verilog码写的CIC滤波器的程序」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cic_filter is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        cic_in          : in     vl_logic_vector(15 downto 0);
        cic_out         : out    vl_logic_vector(39 downto 0);
        rdy             : out    vl_logic
    );
end cic_filter;