scrambler.xml

通信系统中的加扰与解扰程序

<interfaceDefinition version='1.1' language='verilog' kind='module' name='scrambler'>
    <portList>

      <port name='clk' direction='input' type='' />
      <port name='seqIn' direction='input' type='[7:0]' />
      <port name='seqOut' direction='output' type='[7:0]' />
      <port name='en' direction='input' type='' />

    </portList>
</interfaceDefinition>