_primary.vhd

来自「通信系统中的加扰与解扰程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity scrambler is
    port(
        clk             : in     vl_logic;
        seqIn           : in     vl_logic_vector(7 downto 0);
        seqOut          : out    vl_logic_vector(7 downto 0);
        en              : in     vl_logic
    );
end scrambler;