model7_select.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 42 行

module model7_select(l1,l2,l3,l4,c,en1,reset,en,clk,c1,l11,l12,l13,l14);
  output [1:0] l1,l2,l3,l4;
  output c,en1;
  input reset,en,clk,c1;
  input [1:0] l11,l12,l13,l14;
  wire [1:0] l11,l22,l33,l44;
  reg [1:0] l1,l2,l3,l4;
  reg c,en1;
  reg  i;

  always@(posedge clk or negedge reset)
  begin
   if(reset==1'b0)
     begin
      i<=1'b0; en1<=1'b0;  
      l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
     end
   else if(en==1'b1)
        begin
         if(i<1'd1)
           begin
             en1<=1'b1;   
             l1<=l11; l2<=l12; l3<=l13; l4<=l14; c<=1'b0;
             if(c1==1'b1) 
               i<=i+1'b1;
          end
         else if(i==1'd1)
                begin
                  en1<=1'b0;   
                  l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b1;
                  i<=1'b0;
                end
       end
else
  begin
    en1<=1'b0; 
    l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
    i<=1'b0;  
  end
end

endmodule