div_5000.v

一个圣诞彩灯控制芯片的vrilog源代码

//divid frequency module----2
module div_5000(clk_50,reset,clk_250k);
parameter number1=5000;
input  clk_250k,reset;
output clk_50;
reg    clk_50;
reg [12:0] flag;
//initial
    // flag=0;
always @(posedge clk_250k or negedge reset)
if (reset==0)
   flag=13'b0000000000000;
else
 begin 
     if (flag==number1-1)
          begin
            clk_50=1'b1;
            flag=13'b0000000000000;
          end
       else
           begin
              flag=flag+13'b0000000000001;
              clk_50=1'b0;
            end
end
endmodule