tg.v

一个圣诞彩灯控制芯片的vrilog源代码

module TG(l1,l2,l3,l4,ein,reset,tg,clk,I0,I1,I2,I3,I4,I5,I6,I7,
          I8,I9,I10,I11,I12,I13,I14,I15,I16,I17,I18,I19,I20,I21,
          I22,I23,I24,I25,I26,I27,I28,I29,I30,I31);
  output [1:0] l1,l2,l3,l4;
  output [7:0] ein;
  input tg,reset,clk;
  input [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19,I20,I21,I22,I23,
              I24,I25,I26,I27,I28,I29,I30,I31;
  reg [1:0] l1,l2,l3,l4;
  reg [7:0] ein;
  wire tg,reset,clk;
  wire [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
             I8,I9,I10,I11,I12,I13,I14,I15,
             I16,I17,I18,I19,I20,I21,I22,I23,
             I24,I25,I26,I27,I28,I29,I30,I31;
  reg [3:0] flag;

always@(negedge tg or negedge reset)
  begin
    if(reset==1'b0)
       begin
       flag<=4'b0000;
       end
    else if(flag==4'd7)
           flag<=4'b0000;
          else 
            flag<=flag+4'b0001;
  end 

always@(posedge clk or negedge reset)
  begin
   if(reset==1'b0)
     begin
      ein<=8'b00000001;  
      l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00;  
     end
   else  
     begin
         case(flag)
             4'b0000: ein<=8'b00000001;
             4'b0001: ein<=8'b00000010;
             4'b0010: ein<=8'b00000100;
             4'b0011: ein<=8'b00001000;
             4'b0100: ein<=8'b00010000;
             4'b0101: ein<=8'b00100000;
             4'b0110: ein<=8'b01000000;
             4'b0111: ein<=8'b10000000;
             default:  ;
         endcase
          case(ein)
             8'b00000001: begin                       
                           l1<=I0; l2<=I1; l3<=I2; l4<=I3;  
                          end
             8'b00000010: begin
                           l1<=I4; l2<=I5; l3<=I6; l4<=I7;  
                          end
             8'b00000100: begin
                           l1<=I8; l2<=I9; l3<=I10; l4<=I11; 
                          end
             8'b00001000: begin
                           l1<=I12; l2<=I13; l3<=I14; l4<=I15;  
                          end
             8'b00010000: begin
                           l1<=I16; l2<=I17; l3<=I18; l4<=I19;  
                        end
             8'b00100000: begin
                          l1<=I20; l2<=I21; l3<=I22; l4<=I23;  
                        end
             8'b01000000: begin
                          l1<=I24; l2<=I25; l3<=I26; l4<=I27;  
                        end
             8'b10000000: begin
                          l1<=I28; l2<=I29; l3<=I30; l4<=I31;  
                        end
             default:   begin
                          ein<=8'b00000001;
                        end
         endcase
        end
        end
endmodule